Author: Amara Emerson Date: 2021-01-14T19:31:19-08:00 New Revision: 8f283cafddfa8d6d01a94b48cdc5d25817569e91
URL: https://github.com/llvm/llvm-project/commit/8f283cafddfa8d6d01a94b48cdc5d25817569e91 DIFF: https://github.com/llvm/llvm-project/commit/8f283cafddfa8d6d01a94b48cdc5d25817569e91.diff LOG: [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP. In order to import patterns for these, we need to define new ops that can map to the AArch64ISD::[SU]ITOF nodes. We then transform fpr->fpr variants of the generic opcodes to these custom opcodes in preisel-lowering. We have to do it here and not the PostLegalizer combiner because this has to run after regbankselect. Differential Revision: https://reviews.llvm.org/D94702 Added: Modified: llvm/lib/Target/AArch64/AArch64InstrGISel.td llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td index eadb6847ceb6..25656fac1d2f 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td +++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td @@ -146,6 +146,16 @@ def G_VLSHR : AArch64GenericInstruction { let InOperandList = (ins type0:$src1, untyped_imm_0:$imm); } +// Represents an integer to FP conversion on the FPR bank. +def G_SITOF : AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src); +} +def G_UITOF : AArch64GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src); +} + def : GINodeEquiv<G_REV16, AArch64rev16>; def : GINodeEquiv<G_REV32, AArch64rev32>; def : GINodeEquiv<G_REV64, AArch64rev64>; @@ -163,6 +173,8 @@ def : GINodeEquiv<G_TRN2, AArch64trn2>; def : GINodeEquiv<G_EXT, AArch64ext>; def : GINodeEquiv<G_VASHR, AArch64vashr>; def : GINodeEquiv<G_VLSHR, AArch64vlshr>; +def : GINodeEquiv<G_SITOF, AArch64sitof>; +def : GINodeEquiv<G_UITOF, AArch64uitof>; def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 6dc0d1fb97e2..c2e3d9484207 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -1941,6 +1941,24 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) { I.getOperand(1).setReg(NewSrc.getReg(0)); return true; } + case TargetOpcode::G_UITOFP: + case TargetOpcode::G_SITOFP: { + // If both source and destination regbanks are FPR, then convert the opcode + // to G_SITOF so that the importer can select it to an fpr variant. + // Otherwise, it ends up matching an fpr/gpr variant and adding a cross-bank + // copy. + Register SrcReg = I.getOperand(1).getReg(); + if (MRI.getType(SrcReg).isVector()) + return false; + if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) { + if (I.getOpcode() == TargetOpcode::G_SITOFP) + I.setDesc(TII.get(AArch64::G_SITOF)); + else + I.setDesc(TII.get(AArch64::G_UITOF)); + return true; + } + return false; + } default: return false; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir index aea10c5c6c9d..aad71bd99f8f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir @@ -218,7 +218,7 @@ body: | ... --- -name: sitofp_s32_s32_fpr +name: sitofp_s32_s32_fpr_gpr legalized: true regBankSelected: true @@ -230,7 +230,7 @@ body: | bb.0: liveins: $w0 - ; CHECK-LABEL: name: sitofp_s32_s32_fpr + ; CHECK-LABEL: name: sitofp_s32_s32_fpr_gpr ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]] ; CHECK: $s0 = COPY [[SCVTFUWSri]] @@ -239,6 +239,50 @@ body: | $s0 = COPY %1(s32) ... +--- +name: sitofp_s32_s32_fpr_fpr +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + +body: | + bb.0: + liveins: $s0 + + ; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[SCVTFv1i32:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]] + ; CHECK: $s0 = COPY [[SCVTFv1i32]] + %0(s32) = COPY $s0 + %1(s32) = G_SITOFP %0 + $s0 = COPY %1(s32) +... + +--- +name: uitofp_s32_s32_fpr_fpr +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + +body: | + bb.0: + liveins: $s0 + + ; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK: [[UCVTFv1i32:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]] + ; CHECK: $s0 = COPY [[UCVTFv1i32]] + %0(s32) = COPY $s0 + %1(s32) = G_UITOFP %0 + $s0 = COPY %1(s32) +... + --- name: sitofp_s32_s64_fpr legalized: true _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
