Author: Craig Topper Date: 2021-01-10T23:39:08-08:00 New Revision: 131ce834e4bbe443a0da0e0ce00c8d0fa4412458
URL: https://github.com/llvm/llvm-project/commit/131ce834e4bbe443a0da0e0ce00c8d0fa4412458 DIFF: https://github.com/llvm/llvm-project/commit/131ce834e4bbe443a0da0e0ce00c8d0fa4412458.diff LOG: [RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instructions. Remove InstAliases that duplicate the asm strings in the pseudos. The Pseudo class sets isCodeGenOnly=1 which causes the asm strings in the pseudos to be ignored. I think this is why the aliases are needed at all. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94024 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoV.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 339bb68e6601..aa505b22afd8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -628,7 +628,8 @@ def PseudoVMSLT_VI : Pseudo<(outs VR:$vd), [], "vmslt.vi", "$vd, $vs2, $imm$vm">; } -let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, + mayStore = 0 in { def PseudoVMSGEU_VX : Pseudo<(outs VR:$vd), (ins VR:$vs2, GPR:$rs1), [], "vmsgeu.vx", "$vd, $vs2, $rs1">; @@ -649,25 +650,6 @@ def PseudoVMSGE_VX_M_T : Pseudo<(outs VMV0:$vd, VR:$scratch), [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; } -// This apparently unnecessary alias prevents matching `vmsge{u}.vx vd, vs2, vs1` as if -// it were an unmasked (i.e. $vm = RISCV::NoRegister) PseudoVMSGE{U}_VX_M. -def : InstAlias<"vmsgeu.vx $vd, $va, $rs1", - (PseudoVMSGEU_VX VR:$vd, VR:$va, GPR:$rs1), 0>; -def : InstAlias<"vmsge.vx $vd, $va, $rs1", - (PseudoVMSGE_VX VR:$vd, VR:$va, GPR:$rs1), 0>; -def : InstAlias<"vmsgeu.vx v0, $va, $rs1, $vm, $vt", - (PseudoVMSGEU_VX_M_T V0, VR:$vt, VR:$va, GPR:$rs1, - VMaskOp:$vm), 0>; -def : InstAlias<"vmsge.vx v0, $va, $rs1, $vm, $vt", - (PseudoVMSGE_VX_M_T V0, VR:$vt, VR:$va, GPR:$rs1, - VMaskOp:$vm), 0>; -def : InstAlias<"vmsgeu.vx $vd, $va, $rs1, $vm", - (PseudoVMSGEU_VX_M VRNoV0:$vd, VR:$va, GPR:$rs1, - VMaskOp:$vm), 0>; -def : InstAlias<"vmsge.vx $vd, $va, $rs1, $vm", - (PseudoVMSGE_VX_M VRNoV0:$vd, VR:$va, GPR:$rs1, - VMaskOp:$vm), 0>; - // Vector Integer Min/Max Instructions defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>; defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
