Author: Qiu Chaofan Date: 2021-01-08T17:59:13+08:00 New Revision: 6175fcf01f17e0bd1155aaaba977b9baa88ee61d
URL: https://github.com/llvm/llvm-project/commit/6175fcf01f17e0bd1155aaaba977b9baa88ee61d DIFF: https://github.com/llvm/llvm-project/commit/6175fcf01f17e0bd1155aaaba977b9baa88ee61d.diff LOG: [NFC] Update some PPC tests marked as auto-generated Update CodeGen regression tests with marker at first line telling it's auto-generated by the script, under PowerPC directory. For some reason, these tests are generated but manually written, which makes things unclear when someone's change affecting them. However, some tests only show simple change after re-generated, like extra blank lines, disappearing '.localentry', etc. Besides, some tests are generated but added checks for debug output. This commit doesn't try updating them. Added: Modified: llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll llvm/test/CodeGen/PowerPC/maddld.ll llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll llvm/test/CodeGen/PowerPC/pr33547.ll llvm/test/CodeGen/PowerPC/pr35688.ll llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll llvm/test/CodeGen/PowerPC/tls-pie-xform.ll llvm/test/CodeGen/PowerPC/vec_constants.ll llvm/test/CodeGen/PowerPC/vec_int_ext.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll b/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll index 72e17f820adb..8d96a784f2bf 100644 --- a/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll +++ b/llvm/test/CodeGen/PowerPC/lsr-ctrloop.ll @@ -6,15 +6,23 @@ ; for (i = 0; i < 8000; i++) ; data[i] = d; ; } -; +; ; This loop will be unrolled by 96 and vectorized on power9. ; icmp for loop iteration index and loop trip count(384) has LSRUse for 'reg({0,+,384})'. -; Make sure above icmp does not impact LSR choose best formulae sets based on 'reg({(192 + %0),+,384})' +; Make sure above icmp does not impact LSR choose best formulae sets based on 'reg({(192 + %0),+,384})' define void @foo(float* nocapture %data, float %d) { ; CHECK-LABEL: foo: -; CHECK: .LBB0_1: # %vector.body -; CHECK: stxv 0, -192(4) +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li 5, 83 +; CHECK-NEXT: addi 4, 3, 192 +; CHECK-NEXT: xscvdpspn 0, 1 +; CHECK-NEXT: mtctr 5 +; CHECK-NEXT: xxspltw 0, 0, 0 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_1: # %vector.body +; CHECK-NEXT: # +; CHECK-NEXT: stxv 0, -192(4) ; CHECK-NEXT: stxv 0, -176(4) ; CHECK-NEXT: stxv 0, -160(4) ; CHECK-NEXT: stxv 0, -144(4) @@ -40,6 +48,40 @@ define void @foo(float* nocapture %data, float %d) { ; CHECK-NEXT: stxv 0, 176(4) ; CHECK-NEXT: addi 4, 4, 384 ; CHECK-NEXT: bdnz .LBB0_1 +; CHECK-NEXT: # %bb.2: # %for.body +; CHECK-NEXT: stfs 1, 31872(3) +; CHECK-NEXT: stfs 1, 31876(3) +; CHECK-NEXT: stfs 1, 31880(3) +; CHECK-NEXT: stfs 1, 31884(3) +; CHECK-NEXT: stfs 1, 31888(3) +; CHECK-NEXT: stfs 1, 31892(3) +; CHECK-NEXT: stfs 1, 31896(3) +; CHECK-NEXT: stfs 1, 31900(3) +; CHECK-NEXT: stfs 1, 31904(3) +; CHECK-NEXT: stfs 1, 31908(3) +; CHECK-NEXT: stfs 1, 31912(3) +; CHECK-NEXT: stfs 1, 31916(3) +; CHECK-NEXT: stfs 1, 31920(3) +; CHECK-NEXT: stfs 1, 31924(3) +; CHECK-NEXT: stfs 1, 31928(3) +; CHECK-NEXT: stfs 1, 31932(3) +; CHECK-NEXT: stfs 1, 31936(3) +; CHECK-NEXT: stfs 1, 31940(3) +; CHECK-NEXT: stfs 1, 31944(3) +; CHECK-NEXT: stfs 1, 31948(3) +; CHECK-NEXT: stfs 1, 31952(3) +; CHECK-NEXT: stfs 1, 31956(3) +; CHECK-NEXT: stfs 1, 31960(3) +; CHECK-NEXT: stfs 1, 31964(3) +; CHECK-NEXT: stfs 1, 31968(3) +; CHECK-NEXT: stfs 1, 31972(3) +; CHECK-NEXT: stfs 1, 31976(3) +; CHECK-NEXT: stfs 1, 31980(3) +; CHECK-NEXT: stfs 1, 31984(3) +; CHECK-NEXT: stfs 1, 31988(3) +; CHECK-NEXT: stfs 1, 31992(3) +; CHECK-NEXT: stfs 1, 31996(3) +; CHECK-NEXT: blr entry: %broadcast.splatinsert16 = insertelement <4 x float> undef, float %d, i32 0 diff --git a/llvm/test/CodeGen/PowerPC/maddld.ll b/llvm/test/CodeGen/PowerPC/maddld.ll index 3b60a8f88b0b..03ee27a76c94 100644 --- a/llvm/test/CodeGen/PowerPC/maddld.ll +++ b/llvm/test/CodeGen/PowerPC/maddld.ll @@ -1,14 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P9 -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P8 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8 define signext i64 @maddld64(i64 signext %a, i64 signext %b) { -; CHECK-LABEL: maddld64: -; CHECK: # %bb.0: # %entry +; CHECK-P9-LABEL: maddld64: +; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: maddld 3, 4, 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld64: +; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mulld 4, 4, 3 ; CHECK-P8-NEXT: add 3, 4, 3 -; CHECK-NEXT: blr +; CHECK-P8-NEXT: blr entry: %mul = mul i64 %b, %a @@ -17,14 +21,18 @@ entry: } define signext i32 @maddld32(i32 signext %a, i32 signext %b) { -; CHECK-LABEL: maddld32: -; CHECK: # %bb.0: # %entry +; CHECK-P9-LABEL: maddld32: +; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: maddld 3, 4, 3, 3 ; CHECK-P9-NEXT: extsw 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32: +; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mullw 4, 4, 3 ; CHECK-P8-NEXT: add 3, 4, 3 ; CHECK-P8-NEXT: extsw 3, 3 -; CHECK-NEXT: blr +; CHECK-P8-NEXT: blr entry: %mul = mul i32 %b, %a @@ -33,14 +41,18 @@ entry: } define signext i16 @maddld16(i16 signext %a, i16 signext %b, i16 signext %c) { -; CHECK-LABEL: maddld16: -; CHECK: # %bb.0: # %entry +; CHECK-P9-LABEL: maddld16: +; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: maddld 3, 4, 3, 5 ; CHECK-P9-NEXT: extsh 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld16: +; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mullw 3, 4, 3 ; CHECK-P8-NEXT: add 3, 3, 5 ; CHECK-P8-NEXT: extsh 3, 3 -; CHECK-NEXT: blr +; CHECK-P8-NEXT: blr entry: %mul = mul i16 %b, %a @@ -49,13 +61,18 @@ entry: } define zeroext i32 @maddld32zeroext(i32 zeroext %a, i32 zeroext %b) { -; CHECK-LABEL: maddld32zeroext: -; CHECK: # %bb.0: # %entry +; CHECK-P9-LABEL: maddld32zeroext: +; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: maddld 3, 4, 3, 3 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32zeroext: +; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mullw 4, 4, 3 ; CHECK-P8-NEXT: add 3, 4, 3 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr entry: %mul = mul i32 %b, %a @@ -64,13 +81,18 @@ entry: } define signext i32 @maddld32nsw(i32 signext %a, i32 signext %b) { -; CHECK-LABEL: maddld32nsw: -; CHECK: # %bb.0: # %entry +; CHECK-P9-LABEL: maddld32nsw: +; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: maddld 3, 4, 3, 3 +; CHECK-P9-NEXT: extsw 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nsw: +; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mullw 4, 4, 3 ; CHECK-P8-NEXT: add 3, 4, 3 -; CHECK-NEXT: extsw 3, 3 -; CHECK-NEXT: blr +; CHECK-P8-NEXT: extsw 3, 3 +; CHECK-P8-NEXT: blr entry: %mul = mul nsw i32 %b, %a @@ -79,13 +101,18 @@ entry: } define zeroext i32 @maddld32nuw(i32 zeroext %a, i32 zeroext %b) { -; CHECK-LABEL: maddld32nuw: -; CHECK: # %bb.0: # %entry +; CHECK-P9-LABEL: maddld32nuw: +; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: maddld 3, 4, 3, 3 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nuw: +; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mullw 4, 4, 3 ; CHECK-P8-NEXT: add 3, 4, 3 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr entry: %mul = mul nuw i32 %b, %a @@ -94,13 +121,17 @@ entry: } define signext i64 @maddld64_imm(i64 signext %a, i64 signext %b) { -; CHECK-LABEL: maddld64_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mulli 4, 4, 13 -; CHECK-NEXT: add 3, 4, 3 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld64_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulli 4, 4, 13 +; CHECK-P9-NEXT: add 3, 4, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld64_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulli 4, 4, 13 +; CHECK-P8-NEXT: add 3, 4, 3 +; CHECK-P8-NEXT: blr entry: %mul = mul i64 %b, 13 %add = add i64 %mul, %a @@ -108,14 +139,19 @@ entry: } define signext i32 @maddld32_imm(i32 signext %a, i32 signext %b) { -; CHECK-LABEL: maddld32_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mullw 3, 4, 3 -; CHECK-NEXT: addi 3, 3, 13 -; CHECK-NEXT: extsw 3, 3 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld32_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mullw 3, 4, 3 +; CHECK-P9-NEXT: addi 3, 3, 13 +; CHECK-P9-NEXT: extsw 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mullw 3, 4, 3 +; CHECK-P8-NEXT: addi 3, 3, 13 +; CHECK-P8-NEXT: extsw 3, 3 +; CHECK-P8-NEXT: blr entry: %mul = mul i32 %b, %a %add = add i32 %mul, 13 @@ -123,14 +159,19 @@ entry: } define signext i16 @maddld16_imm(i16 signext %a, i16 signext %b, i16 signext %c) { -; CHECK-LABEL: maddld16_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mulli 3, 4, 13 -; CHECK-NEXT: add 3, 3, 5 -; CHECK-NEXT: extsh 3, 3 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld16_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulli 3, 4, 13 +; CHECK-P9-NEXT: add 3, 3, 5 +; CHECK-P9-NEXT: extsh 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld16_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulli 3, 4, 13 +; CHECK-P8-NEXT: add 3, 3, 5 +; CHECK-P8-NEXT: extsh 3, 3 +; CHECK-P8-NEXT: blr entry: %mul = mul i16 %b, 13 %add = add i16 %mul, %c @@ -138,14 +179,19 @@ entry: } define zeroext i32 @maddld32zeroext_imm(i32 zeroext %a, i32 zeroext %b) { -; CHECK-LABEL: maddld32zeroext_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mullw 3, 4, 3 -; CHECK-NEXT: addi 3, 3, 13 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld32zeroext_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mullw 3, 4, 3 +; CHECK-P9-NEXT: addi 3, 3, 13 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32zeroext_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mullw 3, 4, 3 +; CHECK-P8-NEXT: addi 3, 3, 13 +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr entry: %mul = mul i32 %b, %a %add = add i32 %mul, 13 @@ -153,14 +199,19 @@ entry: } define signext i32 @maddld32nsw_imm(i32 signext %a, i32 signext %b) { -; CHECK-LABEL: maddld32nsw_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mulli 4, 4, 13 -; CHECK-NEXT: add 3, 4, 3 -; CHECK-NEXT: extsw 3, 3 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld32nsw_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulli 4, 4, 13 +; CHECK-P9-NEXT: add 3, 4, 3 +; CHECK-P9-NEXT: extsw 3, 3 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nsw_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulli 4, 4, 13 +; CHECK-P8-NEXT: add 3, 4, 3 +; CHECK-P8-NEXT: extsw 3, 3 +; CHECK-P8-NEXT: blr entry: %mul = mul nsw i32 %b, 13 %add = add nsw i32 %mul, %a @@ -168,14 +219,19 @@ entry: } define zeroext i32 @maddld32nuw_imm(i32 zeroext %a, i32 zeroext %b) { -; CHECK-LABEL: maddld32nuw_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mullw 3, 4, 3 -; CHECK-NEXT: addi 3, 3, 13 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld32nuw_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mullw 3, 4, 3 +; CHECK-P9-NEXT: addi 3, 3, 13 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nuw_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mullw 3, 4, 3 +; CHECK-P8-NEXT: addi 3, 3, 13 +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr entry: %mul = mul nuw i32 %b, %a %add = add nuw i32 %mul, 13 @@ -183,14 +239,19 @@ entry: } define zeroext i32 @maddld32nuw_imm_imm(i32 zeroext %b) { -; CHECK-LABEL: maddld32nuw_imm_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: mulli 3, 3, 18 -; CHECK-NEXT: addi 3, 3, 13 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld32nuw_imm_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulli 3, 3, 18 +; CHECK-P9-NEXT: addi 3, 3, 13 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nuw_imm_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulli 3, 3, 18 +; CHECK-P8-NEXT: addi 3, 3, 13 +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr entry: %mul = mul nuw i32 %b, 18 %add = add nuw i32 %mul, 13 @@ -198,16 +259,23 @@ entry: } define zeroext i32 @maddld32nuw_bigimm_imm(i32 zeroext %b) { -; CHECK-LABEL: maddld32nuw_bigimm_imm: -; CHECK: # %bb.0: # %entry -; CHECK-NOT: maddld -; CHECK-NEXT: lis 4, 26127 -; CHECK-NEXT: ori 4, 4, 63251 -; CHECK-NEXT: mullw 3, 3, 4 -; CHECK-NEXT: addi 3, 3, 13 -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr - +; CHECK-P9-LABEL: maddld32nuw_bigimm_imm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: lis 4, 26127 +; CHECK-P9-NEXT: ori 4, 4, 63251 +; CHECK-P9-NEXT: mullw 3, 3, 4 +; CHECK-P9-NEXT: addi 3, 3, 13 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nuw_bigimm_imm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: lis 4, 26127 +; CHECK-P8-NEXT: ori 4, 4, 63251 +; CHECK-P8-NEXT: mullw 3, 3, 4 +; CHECK-P8-NEXT: addi 3, 3, 13 +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr entry: %mul = mul nuw i32 %b, 1712322323 %add = add nuw i32 %mul, 13 @@ -215,22 +283,27 @@ entry: } define zeroext i32 @maddld32nuw_bigimm_bigimm(i32 zeroext %b) { -; CHECK-LABEL: maddld32nuw_bigimm_bigimm: -; CHECK: # %bb.0: # %entry -; CHECK-P9-NEXT: lis 4, -865 -; CHECK-P9-NEXT: lis 5, 26127 -; CHECK-P9-NEXT: ori 4, 4, 42779 -; CHECK-P9-NEXT: ori 5, 5, 63251 -; CHECK-P9-NEXT: maddld 3, 3, 5, 4 - -; CHECK-P8-NEXT: lis 4, 26127 -; CHECK-P8-NEXT: ori 4, 4, 63251 -; CHECK-P8-NEXT: mullw 3, 3, 4 -; CHECK-P8-NEXT: addi 3, 3, -22757 -; CHECK-P8-NEXT: addis 3, 3, -864 - -; CHECK-NEXT: clrldi 3, 3, 32 -; CHECK-NEXT: blr +; CHECK-P9-LABEL: maddld32nuw_bigimm_bigimm: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: lis 4, -865 +; CHECK-P9-NEXT: lis 5, 26127 +; CHECK-P9-NEXT: ori 4, 4, 42779 +; CHECK-P9-NEXT: ori 5, 5, 63251 +; CHECK-P9-NEXT: maddld 3, 3, 5, 4 +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: maddld32nuw_bigimm_bigimm: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: lis 4, 26127 +; CHECK-P8-NEXT: ori 4, 4, 63251 +; CHECK-P8-NEXT: mullw 3, 3, 4 +; CHECK-P8-NEXT: addi 3, 3, -22757 +; CHECK-P8-NEXT: addis 3, 3, -864 +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: blr + + entry: %mul = mul nuw i32 %b, 1712322323 diff --git a/llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll b/llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll index 0e65ebde8d5a..e54dec2fc56b 100644 --- a/llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll +++ b/llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll @@ -3,10 +3,52 @@ ; RUN: -verify-machineinstrs < %s | FileCheck %s define signext i32 @test(i32* noalias %PtrA, i32* noalias %PtrB, i32 signext %LenA, i32 signext %LenB) #0 { ; CHECK-LABEL: test: -; CHECK-NOT: mtctr -; CHECK-NOT: bdnz -; CHECK-NOT: bdz -; CHECK: blr +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li 6, 0 +; CHECK-NEXT: addi 7, 3, 4 +; CHECK-NEXT: addi 4, 4, -4 +; CHECK-NEXT: li 8, 0 +; CHECK-NEXT: .LBB0_1: # %block3 +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB0_2 Depth 2 +; CHECK-NEXT: mr 9, 6 +; CHECK-NEXT: addi 6, 6, 1 +; CHECK-NEXT: extsw 8, 8 +; CHECK-NEXT: cmpw 6, 5 +; CHECK-NEXT: extsw 9, 9 +; CHECK-NEXT: crnot 20, 0 +; CHECK-NEXT: sldi 10, 8, 2 +; CHECK-NEXT: sldi 9, 9, 2 +; CHECK-NEXT: addi 8, 8, 1 +; CHECK-NEXT: add 10, 4, 10 +; CHECK-NEXT: bc 12, 20, .LBB0_5 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_2: # %if.end +; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: lwz 11, 4(10) +; CHECK-NEXT: cmplwi 11, 0 +; CHECK-NEXT: addi 11, 10, 4 +; CHECK-NEXT: beq 0, .LBB0_4 +; CHECK-NEXT: # %bb.3: # %if.then4 +; CHECK-NEXT: # +; CHECK-NEXT: lwzx 12, 7, 9 +; CHECK-NEXT: addi 8, 8, 1 +; CHECK-NEXT: stw 12, 8(10) +; CHECK-NEXT: mr 10, 11 +; CHECK-NEXT: bc 4, 20, .LBB0_2 +; CHECK-NEXT: b .LBB0_5 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_4: # %if.end9 +; CHECK-NEXT: # +; CHECK-NEXT: add 9, 3, 9 +; CHECK-NEXT: lwz 10, 4(9) +; CHECK-NEXT: addi 10, 10, 1 +; CHECK-NEXT: stw 10, 4(9) +; CHECK-NEXT: b .LBB0_1 +; CHECK-NEXT: .LBB0_5: # %if.then +; CHECK-NEXT: lwax 3, 9, 3 +; CHECK-NEXT: blr entry: br label %block2 diff --git a/llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll b/llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll index 1506a35cc508..7a9e58af5913 100644 --- a/llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll +++ b/llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll @@ -94,6 +94,13 @@ entry: } define i64 @andis_no_cmp(i64 %a, i64 %b) { +; CHECK-LABEL: andis_no_cmp: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: andis. 5, 3, 1 +; CHECK-NEXT: li 5, 1 +; CHECK-NEXT: iseleq 4, 4, 5 +; CHECK-NEXT: mulld 3, 4, 3 +; CHECK-NEXT: blr entry: %and = and i64 %a, 65536 %tobool = icmp eq i64 %and, 0 diff --git a/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll b/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll index 8c6df8c5edfb..4762cb946b43 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll @@ -6,23 +6,24 @@ ; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT define dso_local void @foo(i32 %inta, i64* %long_intb) { +; 32BIT-LABEL: foo: +; 32BIT: # %bb.0: # %entry +; 32BIT-NEXT: srawi 5, 3, 31 +; 32BIT-NEXT: rotlwi 6, 3, 8 +; 32BIT-NEXT: slwi 3, 3, 8 +; 32BIT-NEXT: rlwimi 6, 5, 8, 0, 23 +; 32BIT-NEXT: stw 3, 4(4) +; 32BIT-NEXT: stw 6, 0(4) +; 32BIT-NEXT: blr +; +; 64BIT-LABEL: foo: +; 64BIT: # %bb.0: # %entry +; 64BIT-NEXT: extswsli 3, 3, 8 +; 64BIT-NEXT: std 3, 0(4) +; 64BIT-NEXT: blr entry: %conv = sext i32 %inta to i64 %shl = shl nsw i64 %conv, 8 store i64 %shl, i64* %long_intb, align 8 ret void } - -; CHECK-LABEL: foo: - -; 32BIT-DAG: srawi [[REG1:[0-9]+]], [[REG2:[0-9]+]], 31 -; 32BIT-DAG: rotlwi [[REG3:[0-9]+]], [[REG2]], 8 -; 32BIT-DAG: slwi [[REG4:[0-9]+]], [[REG2]], 8 -; 32BIT-DAG: rlwimi [[REG5:[0-9]+]], [[REG1]], 8, 0, 23 -; 32BIT-DAG: stw [[REG4]], 4([[REG6:[0-9]+]]) -; 32BIT-DAG: stw [[REG5]], 0([[REG6]]) -; 32BIT: blr - -; 64BIT: extswsli [[REG1:[0-9]+]], [[REG2:[0-9]+]], 8 -; 64BIT-NEXT: std [[REG1]], 0([[REG3:[0-9]+]]) -; 64BIT-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/pr33547.ll b/llvm/test/CodeGen/PowerPC/pr33547.ll index 166b5c6327ea..67fbab3e3b4e 100644 --- a/llvm/test/CodeGen/PowerPC/pr33547.ll +++ b/llvm/test/CodeGen/PowerPC/pr33547.ll @@ -8,6 +8,24 @@ ; Function Attrs: noinline norecurse nounwind define void @main() { +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %L.entry +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: std 0, 16(1) +; CHECK-NEXT: stdu 1, -32(1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: addis 4, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: ld 4, .LC1@toc@l(4) +; CHECK-NEXT: addi 3, 3, 124 +; CHECK-NEXT: bl testFunc +; CHECK-NEXT: nop +; CHECK-NEXT: addi 1, 1, 32 +; CHECK-NEXT: ld 0, 16(1) +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr L.entry: tail call void @testFunc(i64* bitcast (i8* getelementptr inbounds (%struct.STATICS1, %struct.STATICS1* @.STATICS1, i64 0, i32 0, i64 124) to i64*), i64* bitcast (i32* @.C302_MAIN_ to i64*)) ret void @@ -27,11 +45,46 @@ L.entry: ; Function Attrs: noinline norecurse nounwind define void @testFunc(i64* nocapture %r, i64* nocapture readonly %k) { -; CHECK-LABEL: testFunc -; CHECK: mflr 0 -; CHECK: std 0, 16(1) -; CHECK: bl .[[BRANCHNEXT:[L0-9\$a-z]+]] -; CHECK-NEXT: [[BRANCHNEXT]] +; CHECK-LABEL: testFunc: +; CHECK: # %bb.0: # %L.entry +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: std 0, 16(1) +; CHECK-NEXT: stdu 1, -32(1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: bl .L2$pb +; CHECK-NEXT: .L2$pb: +; CHECK-NEXT: lwz 4, 0(4) +; CHECK-NEXT: mflr 5 +; CHECK-NEXT: addi 4, 4, -1 +; CHECK-NEXT: cmplwi 4, 5 +; CHECK-NEXT: bgt 0, .LBB2_6 +; CHECK-NEXT: # %bb.1: # %L.entry +; CHECK-NEXT: addis 6, 2, .LC2@toc@ha +; CHECK-NEXT: rldic 4, 4, 2, 30 +; CHECK-NEXT: ld 6, .LC2@toc@l(6) +; CHECK-NEXT: lwax 4, 4, 6 +; CHECK-NEXT: add 4, 4, 5 +; CHECK-NEXT: mtctr 4 +; CHECK-NEXT: li 4, -3 +; CHECK-NEXT: bctr +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB2_2: # %infloop11 +; CHECK-NEXT: # +; CHECK-NEXT: b .LBB2_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB2_3: # %infloop +; CHECK-NEXT: # +; CHECK-NEXT: b .LBB2_3 +; CHECK-NEXT: .LBB2_4: # %L.LB3_321.split +; CHECK-NEXT: li 4, 5 +; CHECK-NEXT: .LBB2_5: # %L.LB3_307.sink.split +; CHECK-NEXT: stw 4, 0(3) +; CHECK-NEXT: .LBB2_6: # %L.LB3_307 +; CHECK-NEXT: addi 1, 1, 32 +; CHECK-NEXT: ld 0, 16(1) +; CHECK-NEXT: mtlr 0 +; CHECK-NEXT: blr L.entry: %0 = bitcast i64* %k to i32* %1 = load i32, i32* %0, align 4 diff --git a/llvm/test/CodeGen/PowerPC/pr35688.ll b/llvm/test/CodeGen/PowerPC/pr35688.ll index 3f027abceeeb..2be1add6cdfc 100644 --- a/llvm/test/CodeGen/PowerPC/pr35688.ll +++ b/llvm/test/CodeGen/PowerPC/pr35688.ll @@ -6,29 +6,40 @@ ; Function Attrs: nounwind define void @ec_GFp_nistp256_points_mul() { ; CHECK-LABEL: ec_GFp_nistp256_points_mul: -; CHECK: ld 5, 0(3) -; CHECK: li 3, 127 -; CHECK: li 4, 0 -; CHECK: subfic 6, 5, 0 -; CHECK: subfze 6, 4 -; CHECK: sradi 7, 6, 63 -; CHECK: srad 6, 6, 3 -; CHECK: subc 5, 7, 5 -; CHECK: subfe 5, 4, 6 -; CHECK: sradi 5, 5, 63 +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ld 5, 0(3) +; CHECK-NEXT: li 3, 127 +; CHECK-NEXT: li 4, 0 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_1: # %fe_cmovznz.exit.i534.i.15 +; CHECK-NEXT: # +; CHECK-NEXT: subfic 6, 5, 0 +; CHECK-NEXT: subfze 6, 4 +; CHECK-NEXT: sradi 7, 6, 63 +; CHECK-NEXT: srad 6, 6, 3 +; CHECK-NEXT: subc 5, 7, 5 +; CHECK-NEXT: subfe 5, 4, 6 +; CHECK-NEXT: sradi 5, 5, 63 +; CHECK-NEXT: b .LBB0_1 +; +; MSSA-LABEL: ec_GFp_nistp256_points_mul: +; MSSA: # %bb.0: # %entry +; MSSA-NEXT: ld 3, 0(3) +; MSSA-NEXT: li 4, 0 +; MSSA-NEXT: subfic 5, 3, 0 +; MSSA-NEXT: subfze 5, 4 +; MSSA-NEXT: sradi 5, 5, 63 +; MSSA-NEXT: subc 3, 5, 3 +; MSSA-NEXT: subfe 3, 4, 5 +; MSSA-NEXT: sradi 3, 3, 63 +; MSSA-NEXT: std 3, 0(3) +; MSSA-NEXT: .p2align 4 +; MSSA-NEXT: .LBB0_1: # %fe_cmovznz.exit.i534.i.15 +; MSSA-NEXT: # +; MSSA-NEXT: b .LBB0_1 ; With MemorySSA, everything is taken out of the loop by licm. ; Loads and stores to undef are treated as non-aliasing. -; MSSA-LABEL: ec_GFp_nistp256_points_mul -; MSSA: ld 3, 0(3) -; MSSA: li 4, 0 -; MSSA: subfic 5, 3, 0 -; MSSA: subfze 5, 4 -; MSSA: sradi 5, 5, 63 -; MSSA: subc 3, 5, 3 -; MSSA: subfe 3, 4, 5 -; MSSA: sradi 3, 3, 63 -; MSSA: std 3, 0(3) entry: br label %fe_cmovznz.exit.i534.i.15 diff --git a/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll b/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll index 3874765d75c5..bbb7e5719d8a 100644 --- a/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll +++ b/llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll @@ -342,14 +342,32 @@ declare i64 @llvm.llround.i64.f32(float) define dso_local double @test_nearbyint(double %d) local_unnamed_addr { ; BE-LABEL: test_nearbyint: -; BE: # %bb.0: # %entry -; BE: bl nearbyint -; BE: blr +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: std r0, 16(r1) +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl nearbyint +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr ; ; CHECK-LABEL: test_nearbyint: -; CHECK: # %bb.0: # %entry -; CHECK: bl nearbyint -; CHECK: blr +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -32(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: bl nearbyint +; CHECK-NEXT: nop +; CHECK-NEXT: addi r1, r1, 32 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr ; ; FAST-LABEL: test_nearbyint: ; FAST: # %bb.0: # %entry @@ -364,14 +382,32 @@ declare double @llvm.nearbyint.f64(double) define dso_local float @test_nearbyintf(float %f) local_unnamed_addr { ; BE-LABEL: test_nearbyintf: -; BE: # %bb.0: # %entry -; BE: bl nearbyint -; BE: blr +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: std r0, 16(r1) +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: .cfi_def_cfa_offset 112 +; BE-NEXT: .cfi_offset lr, 16 +; BE-NEXT: bl nearbyintf +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr ; ; CHECK-LABEL: test_nearbyintf: -; CHECK: # %bb.0: # %entry -; CHECK: bl nearbyintf -; CHECK: blr +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -32(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: bl nearbyintf +; CHECK-NEXT: nop +; CHECK-NEXT: addi r1, r1, 32 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr ; ; FAST-LABEL: test_nearbyintf: ; FAST: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/PowerPC/tls-pie-xform.ll b/llvm/test/CodeGen/PowerPC/tls-pie-xform.ll index b6a2c80a2a2e..92b0ae380597 100644 --- a/llvm/test/CodeGen/PowerPC/tls-pie-xform.ll +++ b/llvm/test/CodeGen/PowerPC/tls-pie-xform.ll @@ -9,9 +9,10 @@ define dso_local zeroext i8 @test_char_one() { ; CHECK-LABEL: test_char_one: ; CHECK: # %bb.0: # %entry -; CHECK: addis 3, 2, var_char@got@tprel@ha +; CHECK-NEXT: addis 3, 2, var_char@got@tprel@ha ; CHECK-NEXT: ld 3, var_char@got@tprel@l(3) ; CHECK-NEXT: lbzx 3, 3, var_char@tls +; CHECK-NEXT: blr entry: %0 = load i8, i8* @var_char, align 1, !tbaa !4 ret i8 %0 @@ -20,9 +21,10 @@ entry: define dso_local void @test_char_two(i32 signext %a) { ; CHECK-LABEL: test_char_two: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_char@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_char@got@tprel@ha ; CHECK-NEXT: ld 4, var_char@got@tprel@l(4) ; CHECK-NEXT: stbx 3, 4, var_char@tls +; CHECK-NEXT: blr entry: %conv = trunc i32 %a to i8 store i8 %conv, i8* @var_char, align 1, !tbaa !4 @@ -32,10 +34,13 @@ entry: define dso_local zeroext i8 @test_char_three(i8 zeroext %a) { ; CHECK-LABEL: test_char_three: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_char@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_char@got@tprel@ha ; CHECK-NEXT: ld 4, var_char@got@tprel@l(4) ; CHECK-NEXT: lbzx 5, 4, var_char@tls -; CHECK: stbx {{[0-9]+}}, 4, var_char@tls +; CHECK-NEXT: add 5, 5, 3 +; CHECK-NEXT: clrldi 3, 5, 56 +; CHECK-NEXT: stbx 5, 4, var_char@tls +; CHECK-NEXT: blr entry: %0 = load i8, i8* @var_char, align 1, !tbaa !4 %add = add i8 %0, %a @@ -46,9 +51,10 @@ entry: define dso_local signext i16 @test_short_one() { ; CHECK-LABEL: test_short_one: ; CHECK: # %bb.0: # %entry -; CHECK: addis 3, 2, var_short@got@tprel@ha +; CHECK-NEXT: addis 3, 2, var_short@got@tprel@ha ; CHECK-NEXT: ld 3, var_short@got@tprel@l(3) ; CHECK-NEXT: lhzx 3, 3, var_short@tls +; CHECK-NEXT: blr entry: %0 = load i16, i16* @var_short, align 2, !tbaa !7 ret i16 %0 @@ -57,9 +63,10 @@ entry: define dso_local void @test_short_two(i32 signext %a) { ; CHECK-LABEL: test_short_two: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_short@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_short@got@tprel@ha ; CHECK-NEXT: ld 4, var_short@got@tprel@l(4) ; CHECK-NEXT: sthx 3, 4, var_short@tls +; CHECK-NEXT: blr entry: %conv = trunc i32 %a to i16 store i16 %conv, i16* @var_short, align 2, !tbaa !7 @@ -69,10 +76,13 @@ entry: define dso_local signext i16 @test_short_three(i16 signext %a) { ; CHECK-LABEL: test_short_three: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_short@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_short@got@tprel@ha ; CHECK-NEXT: ld 4, var_short@got@tprel@l(4) ; CHECK-NEXT: lhzx 5, 4, var_short@tls -; CHECK: sthx {{[0-9]+}}, 4, var_short@tls +; CHECK-NEXT: add 5, 5, 3 +; CHECK-NEXT: extsh 3, 5 +; CHECK-NEXT: sthx 5, 4, var_short@tls +; CHECK-NEXT: blr entry: %0 = load i16, i16* @var_short, align 2, !tbaa !7 %add = add i16 %0, %a @@ -83,9 +93,10 @@ entry: define dso_local signext i32 @test_int_one() { ; CHECK-LABEL: test_int_one: ; CHECK: # %bb.0: # %entry -; CHECK: addis 3, 2, var_int@got@tprel@ha +; CHECK-NEXT: addis 3, 2, var_int@got@tprel@ha ; CHECK-NEXT: ld 3, var_int@got@tprel@l(3) ; CHECK-NEXT: lwzx 3, 3, var_int@tls +; CHECK-NEXT: blr entry: %0 = load i32, i32* @var_int, align 4, !tbaa !9 ret i32 %0 @@ -94,9 +105,10 @@ entry: define dso_local void @test_int_two(i32 signext %a) { ; CHECK-LABEL: test_int_two: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_int@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_int@got@tprel@ha ; CHECK-NEXT: ld 4, var_int@got@tprel@l(4) ; CHECK-NEXT: stwx 3, 4, var_int@tls +; CHECK-NEXT: blr entry: store i32 %a, i32* @var_int, align 4, !tbaa !9 ret void @@ -105,10 +117,13 @@ entry: define dso_local signext i32 @test_int_three(i32 signext %a) { ; CHECK-LABEL: test_int_three: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_int@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_int@got@tprel@ha ; CHECK-NEXT: ld 4, var_int@got@tprel@l(4) ; CHECK-NEXT: lwzx 5, 4, var_int@tls -; CHECK: stwx {{[0-9]+}}, 4, var_int@tls +; CHECK-NEXT: add 5, 5, 3 +; CHECK-NEXT: extsw 3, 5 +; CHECK-NEXT: stwx 5, 4, var_int@tls +; CHECK-NEXT: blr entry: %0 = load i32, i32* @var_int, align 4, !tbaa !9 %add = add nsw i32 %0, %a @@ -119,9 +134,10 @@ entry: define dso_local i64 @test_longlong_one() { ; CHECK-LABEL: test_longlong_one: ; CHECK: # %bb.0: # %entry -; CHECK: addis 3, 2, var_long_long@got@tprel@ha +; CHECK-NEXT: addis 3, 2, var_long_long@got@tprel@ha ; CHECK-NEXT: ld 3, var_long_long@got@tprel@l(3) ; CHECK-NEXT: ldx 3, 3, var_long_long@tls +; CHECK-NEXT: blr entry: %0 = load i64, i64* @var_long_long, align 8, !tbaa !11 ret i64 %0 @@ -130,9 +146,10 @@ entry: define dso_local void @test_longlong_two(i32 signext %a) { ; CHECK-LABEL: test_longlong_two: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_long_long@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_long_long@got@tprel@ha ; CHECK-NEXT: ld 4, var_long_long@got@tprel@l(4) ; CHECK-NEXT: stdx 3, 4, var_long_long@tls +; CHECK-NEXT: blr entry: %conv = sext i32 %a to i64 store i64 %conv, i64* @var_long_long, align 8, !tbaa !11 @@ -142,10 +159,12 @@ entry: define dso_local i64 @test_longlong_three(i64 %a) { ; CHECK-LABEL: test_longlong_three: ; CHECK: # %bb.0: # %entry -; CHECK: addis 4, 2, var_long_long@got@tprel@ha +; CHECK-NEXT: addis 4, 2, var_long_long@got@tprel@ha ; CHECK-NEXT: ld 4, var_long_long@got@tprel@l(4) ; CHECK-NEXT: ldx 5, 4, var_long_long@tls -; CHECK: stdx {{[0-9]+}}, 4, var_long_long@tls +; CHECK-NEXT: add 3, 5, 3 +; CHECK-NEXT: stdx 3, 4, var_long_long@tls +; CHECK-NEXT: blr entry: %0 = load i64, i64* @var_long_long, align 8, !tbaa !11 %add = add nsw i64 %0, %a diff --git a/llvm/test/CodeGen/PowerPC/vec_constants.ll b/llvm/test/CodeGen/PowerPC/vec_constants.ll index 71f448ee66b2..eadd704113a4 100644 --- a/llvm/test/CodeGen/PowerPC/vec_constants.ll +++ b/llvm/test/CodeGen/PowerPC/vec_constants.ll @@ -1,8 +1,37 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE +; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { +; BE-LABEL: test1: +; BE: # %bb.0: +; BE-NEXT: lxvw4x 0, 0, 3 +; BE-NEXT: vspltisb 2, -1 +; BE-NEXT: vslw 2, 2, 2 +; BE-NEXT: xxland 0, 0, 34 +; BE-NEXT: stxvw4x 0, 0, 3 +; BE-NEXT: lxvw4x 0, 0, 4 +; BE-NEXT: xxlandc 0, 0, 34 +; BE-NEXT: stxvw4x 0, 0, 4 +; BE-NEXT: lxvw4x 0, 0, 5 +; BE-NEXT: xvabssp 0, 0 +; BE-NEXT: stxvw4x 0, 0, 5 +; BE-NEXT: blr +; +; LE-LABEL: test1: +; LE: # %bb.0: +; LE-NEXT: lvx 2, 0, 3 +; LE-NEXT: vspltisb 3, -1 +; LE-NEXT: vslw 3, 3, 3 +; LE-NEXT: xxland 34, 34, 35 +; LE-NEXT: stvx 2, 0, 3 +; LE-NEXT: lvx 2, 0, 4 +; LE-NEXT: xxlandc 34, 34, 35 +; LE-NEXT: stvx 2, 0, 4 +; LE-NEXT: lvx 2, 0, 5 +; LE-NEXT: xvabssp 34, 34 +; LE-NEXT: stvx 2, 0, 5 +; LE-NEXT: blr %tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] store <4 x i32> %tmp4, <4 x i32>* %P1 @@ -16,8 +45,6 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { store <4 x float> %tmp13, <4 x float>* %P3 ret void -; CHECK-LABEL: test1: -; CHECK-NOT: CPI } define <4 x i32> @test_30() nounwind { diff --git a/llvm/test/CodeGen/PowerPC/vec_int_ext.ll b/llvm/test/CodeGen/PowerPC/vec_int_ext.ll index 1c86e38d0604..e833b2527245 100644 --- a/llvm/test/CodeGen/PowerPC/vec_int_ext.ll +++ b/llvm/test/CodeGen/PowerPC/vec_int_ext.ll @@ -7,9 +7,13 @@ define <4 x i32> @vextsb2wLE(<16 x i8> %a) { ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: vextsb2wLE: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr @@ -34,9 +38,13 @@ define <2 x i64> @vextsb2dLE(<16 x i8> %a) { ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: vextsb2dLE: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: addi 3, 3, .LCPI1_0@toc@l +; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr @@ -55,9 +63,13 @@ define <4 x i32> @vextsh2wLE(<8 x i16> %a) { ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: vextsh2wLE: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; CHECK-BE-NEXT: addi 3, 3, .LCPI2_0@toc@l +; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr @@ -82,9 +94,13 @@ define <2 x i64> @vextsh2dLE(<8 x i16> %a) { ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: vextsh2dLE: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; CHECK-BE-NEXT: addi 3, 3, .LCPI3_0@toc@l +; CHECK-BE-NEXT: lxvx 35, 0, 3 +; CHECK-BE-NEXT: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr @@ -103,9 +119,10 @@ define <2 x i64> @vextsw2dLE(<4 x i32> %a) { ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsw2d 2, 2 ; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: vextsw2dLE: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE: vmrgew +; CHECK-BE-NEXT: vmrgew 2, 2, 2 ; CHECK-BE-NEXT: vextsw2d 2, 2 ; CHECK-BE-NEXT: blr @@ -120,15 +137,16 @@ entry: } define <4 x i32> @vextsb2wBE(<16 x i8> %a) { -; CHECK-BE-LABEL: vextsb2wBE: -; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextsb2w 2, 2 -; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsb2wBE: ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 13 ; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: vextsb2wBE: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextsb2w 2, 2 +; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %a, i32 3 %conv = sext i8 %vecext to i32 @@ -146,15 +164,16 @@ entry: } define <2 x i64> @vextsb2dBE(<16 x i8> %a) { -; CHECK-BE-LABEL: vextsb2dBE: -; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextsb2d 2, 2 -; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsb2dBE: ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 9 ; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: vextsb2dBE: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextsb2d 2, 2 +; CHECK-BE-NEXT: blr entry: %vecext = extractelement <16 x i8> %a, i32 7 %conv = sext i8 %vecext to i64 @@ -166,15 +185,16 @@ entry: } define <4 x i32> @vextsh2wBE(<8 x i16> %a) { -; CHECK-BE-LABEL: vextsh2wBE: -; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextsh2w 2, 2 -; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsh2wBE: ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 14 ; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: vextsh2wBE: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextsh2w 2, 2 +; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %a, i32 1 %conv = sext i16 %vecext to i32 @@ -192,15 +212,16 @@ entry: } define <2 x i64> @vextsh2dBE(<8 x i16> %a) { -; CHECK-BE-LABEL: vextsh2dBE: -; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextsh2d 2, 2 -; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsh2dBE: ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 10 ; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: vextsh2dBE: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextsh2d 2, 2 +; CHECK-BE-NEXT: blr entry: %vecext = extractelement <8 x i16> %a, i32 3 %conv = sext i16 %vecext to i64 @@ -212,15 +233,16 @@ entry: } define <2 x i64> @vextsw2dBE(<4 x i32> %a) { -; CHECK-BE-LABEL: vextsw2dBE: -; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: vextsw2d 2, 2 -; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsw2dBE: ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 12 ; CHECK-LE-NEXT: vextsw2d 2, 2 ; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: vextsw2dBE: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: vextsw2d 2, 2 +; CHECK-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %a, i32 1 %conv = sext i32 %vecext to i64 @@ -234,11 +256,25 @@ entry: define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LE-LABEL: vextDiffVectors: ; CHECK-LE: # %bb.0: # %entry -; CHECK-LE-NOT: vextsw2d - +; CHECK-LE-NEXT: li 3, 0 +; CHECK-LE-NEXT: mfvsrwz 4, 35 +; CHECK-LE-NEXT: vextuwrx 3, 3, 2 +; CHECK-LE-NEXT: extsw 4, 4 +; CHECK-LE-NEXT: extsw 3, 3 +; CHECK-LE-NEXT: mtvsrdd 34, 4, 3 +; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: vextDiffVectors: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NOT: vextsw2d +; CHECK-BE-NEXT: li 3, 0 +; CHECK-BE-NEXT: li 4, 8 +; CHECK-BE-NEXT: vextuwlx 3, 3, 2 +; CHECK-BE-NEXT: vextuwlx 4, 4, 3 +; CHECK-BE-NEXT: extsw 3, 3 +; CHECK-BE-NEXT: extsw 4, 4 +; CHECK-BE-NEXT: mtvsrdd 34, 3, 4 +; CHECK-BE-NEXT: blr + entry: %vecext = extractelement <4 x i32> %a, i32 0 %conv = sext i32 %vecext to i64 @@ -250,14 +286,101 @@ entry: } define <8 x i16> @testInvalidExtend(<16 x i8> %a) { -entry: ; CHECK-LE-LABEL: testInvalidExtend: ; CHECK-LE: # %bb.0: # %entry -; CHECK-LE-NOT: vexts - +; CHECK-LE-NEXT: li 3, 0 +; CHECK-LE-NEXT: li 4, 2 +; CHECK-LE-NEXT: li 5, 4 +; CHECK-LE-NEXT: li 6, 6 +; CHECK-LE-NEXT: vextubrx 3, 3, 2 +; CHECK-LE-NEXT: vextubrx 4, 4, 2 +; CHECK-LE-NEXT: vextubrx 5, 5, 2 +; CHECK-LE-NEXT: vextubrx 6, 6, 2 +; CHECK-LE-NEXT: li 7, 8 +; CHECK-LE-NEXT: li 8, 10 +; CHECK-LE-NEXT: li 9, 12 +; CHECK-LE-NEXT: li 10, 14 +; CHECK-LE-NEXT: extsb 3, 3 +; CHECK-LE-NEXT: extsb 4, 4 +; CHECK-LE-NEXT: extsb 5, 5 +; CHECK-LE-NEXT: extsb 6, 6 +; CHECK-LE-NEXT: vextubrx 7, 7, 2 +; CHECK-LE-NEXT: vextubrx 8, 8, 2 +; CHECK-LE-NEXT: extsb 7, 7 +; CHECK-LE-NEXT: extsb 8, 8 +; CHECK-LE-NEXT: mtvsrd 35, 4 +; CHECK-LE-NEXT: vextubrx 9, 9, 2 +; CHECK-LE-NEXT: vextubrx 10, 10, 2 +; CHECK-LE-NEXT: mtvsrd 34, 3 +; CHECK-LE-NEXT: mtvsrd 36, 6 +; CHECK-LE-NEXT: extsb 9, 9 +; CHECK-LE-NEXT: extsb 10, 10 +; CHECK-LE-NEXT: mtvsrd 37, 10 +; CHECK-LE-NEXT: vmrghh 2, 3, 2 +; CHECK-LE-NEXT: mtvsrd 35, 5 +; CHECK-LE-NEXT: vmrghh 3, 4, 3 +; CHECK-LE-NEXT: mtvsrd 36, 8 +; CHECK-LE-NEXT: vmrglw 2, 3, 2 +; CHECK-LE-NEXT: mtvsrd 35, 7 +; CHECK-LE-NEXT: vmrghh 3, 4, 3 +; CHECK-LE-NEXT: mtvsrd 36, 9 +; CHECK-LE-NEXT: vmrghh 4, 5, 4 +; CHECK-LE-NEXT: vmrglw 3, 4, 3 +; CHECK-LE-NEXT: xxmrgld 34, 35, 34 +; CHECK-LE-NEXT: blr +; ; CHECK-BE-LABEL: testInvalidExtend: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NOT: vexts +; CHECK-BE-NEXT: li 9, 12 +; CHECK-BE-NEXT: li 10, 14 +; CHECK-BE-NEXT: li 7, 8 +; CHECK-BE-NEXT: li 8, 10 +; CHECK-BE-NEXT: vextublx 9, 9, 2 +; CHECK-BE-NEXT: vextublx 10, 10, 2 +; CHECK-BE-NEXT: vextublx 7, 7, 2 +; CHECK-BE-NEXT: vextublx 8, 8, 2 +; CHECK-BE-NEXT: li 3, 0 +; CHECK-BE-NEXT: li 4, 2 +; CHECK-BE-NEXT: li 5, 4 +; CHECK-BE-NEXT: li 6, 6 +; CHECK-BE-NEXT: extsb 9, 9 +; CHECK-BE-NEXT: extsb 10, 10 +; CHECK-BE-NEXT: extsb 7, 7 +; CHECK-BE-NEXT: extsb 8, 8 +; CHECK-BE-NEXT: vextublx 3, 3, 2 +; CHECK-BE-NEXT: vextublx 4, 4, 2 +; CHECK-BE-NEXT: extsb 3, 3 +; CHECK-BE-NEXT: extsb 4, 4 +; CHECK-BE-NEXT: sldi 10, 10, 48 +; CHECK-BE-NEXT: sldi 9, 9, 48 +; CHECK-BE-NEXT: vextublx 5, 5, 2 +; CHECK-BE-NEXT: vextublx 6, 6, 2 +; CHECK-BE-NEXT: sldi 8, 8, 48 +; CHECK-BE-NEXT: sldi 7, 7, 48 +; CHECK-BE-NEXT: extsb 5, 5 +; CHECK-BE-NEXT: extsb 6, 6 +; CHECK-BE-NEXT: sldi 6, 6, 48 +; CHECK-BE-NEXT: sldi 5, 5, 48 +; CHECK-BE-NEXT: sldi 4, 4, 48 +; CHECK-BE-NEXT: sldi 3, 3, 48 +; CHECK-BE-NEXT: mtvsrd 34, 10 +; CHECK-BE-NEXT: mtvsrd 35, 9 +; CHECK-BE-NEXT: mtvsrd 36, 7 +; CHECK-BE-NEXT: mtvsrd 37, 3 +; CHECK-BE-NEXT: vmrghh 2, 3, 2 +; CHECK-BE-NEXT: mtvsrd 35, 8 +; CHECK-BE-NEXT: vmrghh 3, 4, 3 +; CHECK-BE-NEXT: mtvsrd 36, 5 +; CHECK-BE-NEXT: vmrghw 2, 3, 2 +; CHECK-BE-NEXT: mtvsrd 35, 6 +; CHECK-BE-NEXT: vmrghh 3, 4, 3 +; CHECK-BE-NEXT: mtvsrd 36, 4 +; CHECK-BE-NEXT: vmrghh 4, 5, 4 +; CHECK-BE-NEXT: vmrghw 3, 4, 3 +; CHECK-BE-NEXT: xxmrghd 34, 35, 34 +; CHECK-BE-NEXT: blr +entry: + %vecext = extractelement <16 x i8> %a, i32 0 %conv = sext i8 %vecext to i16 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
