Author: Craig Topper Date: 2021-01-04T12:21:35-08:00 New Revision: fe597efc30b22bac5b49ffb64e52300d661c7d78
URL: https://github.com/llvm/llvm-project/commit/fe597efc30b22bac5b49ffb64e52300d661c7d78 DIFF: https://github.com/llvm/llvm-project/commit/fe597efc30b22bac5b49ffb64e52300d661c7d78.diff LOG: [RISCV] Remove unused method RISCVInstPrinter::printSImm5Plus1. NFC simm5_plus1 is only used by InstAliases so should never be printed. Added: Modified: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h llvm/lib/Target/RISCV/RISCVInstrInfoV.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 7e4590456621..65edd3b4d4f6 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -187,15 +187,6 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, O << ".t"; } -void RISCVInstPrinter::printSImm5Plus1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNo); - - assert(MO.isImm() && "printSImm5Plus1 can only print constant operands"); - O << MO.getImm() + 1; -} - const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) { return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index ddffcbe343d7..d078ead2c8ad 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -46,8 +46,6 @@ class RISCVInstPrinter : public MCInstPrinter { raw_ostream &O); void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printSImm5Plus1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); // Autogenerated by tblgen. std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index b015ae0d2dba..edcde5fbbb39 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -69,7 +69,6 @@ def SImm5Plus1AsmOperand : AsmOperandClass { def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm - 1);}]> { let ParserMatchClass = SImm5Plus1AsmOperand; - let PrintMethod = "printSImm5Plus1"; let MCOperandPredicate = [{ int64_t Imm; if (MCOp.evaluateAsConstantImm(Imm)) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
