Author: David Sherwood Date: 2021-01-04T09:11:05Z New Revision: a65092040ad4fefcdad18382781090839cad3b67
URL: https://github.com/llvm/llvm-project/commit/a65092040ad4fefcdad18382781090839cad3b67 DIFF: https://github.com/llvm/llvm-project/commit/a65092040ad4fefcdad18382781090839cad3b67.diff LOG: [SVE] Fix inline assembly parsing crash This patch fixes a crash encountered when compiling this code: ... float16_t a; __asm__("fminv %h[a], %[b], %[c].h" : [a] "=r" (a) : [b] "Upl" (b), [c] "w" (c)) The issue here is when using the 'h' modifier for a register constraint 'r'. Differential Revision: https://reviews.llvm.org/D93537 Added: Modified: llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index c18e9a4e6db1..c7fa49c965a8 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -647,7 +647,8 @@ bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO, const TargetRegisterInfo *RI = STI->getRegisterInfo(); Register Reg = MO.getReg(); unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg)); - assert(RI->regsOverlap(RegToPrint, Reg)); + if (!RI->regsOverlap(RegToPrint, Reg)) + return true; O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName); return false; } diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll index 5a2f4746af87..aa25d118c9b5 100644 --- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll +++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll @@ -6,6 +6,7 @@ target triple = "aarch64-unknown-linux-gnu" ; CHECK: error: couldn't allocate input reg for constraint 'Upa' ; CHECK: error: couldn't allocate input reg for constraint 'r' ; CHECK: error: couldn't allocate output register for constraint 'w' +; CHECK: error: unknown token in expression define <vscale x 16 x i1> @foo1(i32 *%in) { entry: @@ -27,3 +28,11 @@ entry: %1 = call <vscale x 16 x i1> asm sideeffect "mov $0.b, $1.b \0A", "=&w,w"(<vscale x 16 x i1> %0) ret <vscale x 16 x i1> %1 } + +define half @foo4(<vscale x 16 x i1> *%inp, <vscale x 8 x half> *%inv) { +entry: + %0 = load <vscale x 16 x i1>, <vscale x 16 x i1>* %inp, align 2 + %1 = load <vscale x 8 x half>, <vscale x 8 x half>* %inv, align 16 + %2 = call half asm "fminv ${0:h}, $1, $2.h", "=r,@3Upl,w"(<vscale x 16 x i1> %0, <vscale x 8 x half> %1) + ret half %2 +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
