Author: Amara Emerson Date: 2020-12-25T00:31:47-08:00 New Revision: e0721a0992288122d62940f622b4c2127098a2da
URL: https://github.com/llvm/llvm-project/commit/e0721a0992288122d62940f622b4c2127098a2da DIFF: https://github.com/llvm/llvm-project/commit/e0721a0992288122d62940f622b4c2127098a2da.diff LOG: [AArch64][GlobalISel] Notify observer of mutated instruction for shift custom legalization. No test for this because it's a CSE verifier failure that's only exposed in a WIP patch for enabling CSE throughout the AArch64 GISel pipeline. Added: Modified: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 0774f7b02dd2..a611d68cb2e5 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -841,7 +841,9 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr( if (Amount > 31) return true; // This will have to remain a register variant. auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount); + Observer.changingInstr(MI); MI.getOperand(2).setReg(ExtCst.getReg(0)); + Observer.changedInstr(MI); return true; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
