Author: Stanislav Mekhanoshin Date: 2020-12-23T14:43:31-08:00 New Revision: 747f67e034a924cf308f4c0f1bb6b1fa46bd9fbe
URL: https://github.com/llvm/llvm-project/commit/747f67e034a924cf308f4c0f1bb6b1fa46bd9fbe DIFF: https://github.com/llvm/llvm-project/commit/747f67e034a924cf308f4c0f1bb6b1fa46bd9fbe.diff LOG: [AMDGPU] Fix adjustWritemask subreg handling If we happen to extract a non-dword subreg that breaks the logic of the function and it may shrink the dmask because it does not recognize the use of a lane(s). This bug is next to impossible to trigger with the current lowering in the BE, but it breaks in one of my future patches. Differential Revision: https://reviews.llvm.org/D93782 Added: Modified: llvm/lib/Target/AMDGPU/SIISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 81fdfa0343b3..c7abc585d0d1 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10862,7 +10862,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, /// Helper function for adjustWritemask static unsigned SubIdx2Lane(unsigned Idx) { switch (Idx) { - default: return 0; + default: return ~0u; case AMDGPU::sub0: return 0; case AMDGPU::sub1: return 1; case AMDGPU::sub2: return 2; @@ -10922,6 +10922,8 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit // set, etc. Lane = SubIdx2Lane(I->getConstantOperandVal(1)); + if (Lane == ~0u) + return Node; // Check if the use is for the TFE/LWE generated result at VGPRn+1. if (UsesTFC && Lane == TFCLane) { _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
