Author: Craig Topper Date: 2020-12-16T20:56:14-08:00 New Revision: 541e476fc0682e71d70f6cfc7a42592910acf2a5
URL: https://github.com/llvm/llvm-project/commit/541e476fc0682e71d70f6cfc7a42592910acf2a5 DIFF: https://github.com/llvm/llvm-project/commit/541e476fc0682e71d70f6cfc7a42592910acf2a5.diff LOG: [RISCV] Infer mask type from data type for vector vle and vse intrinsics. The mask type should have the same number of elements as the data type. Similar to D93409 which did this for arithmetic intrinsics. Added: Modified: llvm/include/llvm/IR/IntrinsicsRISCV.td Removed: ################################################################################ diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 6513617a85fc..f5c933c51706 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -92,7 +92,8 @@ let TargetPrefix = "riscv" in { : Intrinsic<[llvm_anyvector_ty ], [LLVMMatchType<0>, LLVMPointerType<LLVMMatchType<0>>, - llvm_anyvector_ty, llvm_anyint_ty], + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, + llvm_anyint_ty], [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic; // For unit stride store // Input: (vector_in, pointer, vl) @@ -108,7 +109,8 @@ let TargetPrefix = "riscv" in { : Intrinsic<[], [llvm_anyvector_ty, LLVMPointerType<LLVMMatchType<0>>, - llvm_anyvector_ty, llvm_anyint_ty], + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, + llvm_anyint_ty], [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic; // For destination vector type is the same as first source vector. // Input: (vector_in, vector_in/scalar_in, vl) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
