Author: Craig Topper Date: 2020-12-16T20:18:30-08:00 New Revision: 0d7dd026c89baa3f8542ae267d26f55fada36717
URL: https://github.com/llvm/llvm-project/commit/0d7dd026c89baa3f8542ae267d26f55fada36717 DIFF: https://github.com/llvm/llvm-project/commit/0d7dd026c89baa3f8542ae267d26f55fada36717.diff LOG: [RISCV] Infer mask type for vector intrinsics from the data type We can use LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> to infer the mask type from the anyvector_ty. This will save us from needing to pass it to getDeclaration when creating these intrinsics from clang. No tests updates are needed because our declarations are exploiting a behavior in the IR parser where the declaration of an intrinsic doesn't need to mention all the types as long as there isn't a name conflict in the file. Reviewed By: khchen Differential Revision: https://reviews.llvm.org/D93409 Added: Modified: llvm/include/llvm/IR/IntrinsicsRISCV.td Removed: ################################################################################ diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index bb695befd13d..6513617a85fc 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -124,7 +124,7 @@ let TargetPrefix = "riscv" in { class RISCVBinaryAAXMask : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty, - llvm_anyvector_ty, llvm_anyint_ty], + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { let ExtendOperand = 3; } @@ -141,7 +141,7 @@ let TargetPrefix = "riscv" in { class RISCVBinaryABXMask : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty, - llvm_anyvector_ty, llvm_anyint_ty], + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { let ExtendOperand = 3; } @@ -149,7 +149,8 @@ let TargetPrefix = "riscv" in { // Input: (vector_in, vector_in/scalar_in, V0, vl) class RISCVBinaryWithV0 : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, + [LLVMMatchType<0>, llvm_any_ty, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { let ExtendOperand = 2; @@ -158,8 +159,9 @@ let TargetPrefix = "riscv" in { // Output: (mask type output) // Input: (vector_in, vector_in/scalar_in, V0, vl) class RISCVBinaryMOutWithV0 - :Intrinsic<[llvm_anyvector_ty], - [llvm_anyvector_ty, llvm_any_ty, LLVMMatchType<0>, + :Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], + [llvm_anyvector_ty, llvm_any_ty, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { let ExtendOperand = 2; @@ -168,7 +170,7 @@ let TargetPrefix = "riscv" in { // Output: (mask type output) // Input: (vector_in, vector_in/scalar_in, vl) class RISCVBinaryMOut - : Intrinsic<[llvm_anyvector_ty], + : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { let ExtendOperand = 2; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
