Author: Craig Topper Date: 2020-12-08T10:23:37-08:00 New Revision: 3e86fbc97189366866aac4286fb9c412c1fb526c
URL: https://github.com/llvm/llvm-project/commit/3e86fbc97189366866aac4286fb9c412c1fb526c DIFF: https://github.com/llvm/llvm-project/commit/3e86fbc97189366866aac4286fb9c412c1fb526c.diff LOG: [RISCV] Replace custom isel code for RISCVISD::READ_CYCLE_WIDE with isel pattern This node returns 2 results and uses a chain. As long as we use a DAG as part of the pseudo instruction definition where we can use the "set" operator, it looks like tablegen can handle use a pattern for this without a problem. I believe the original implementation was copied from PowerPC. This also fixes the pseudo instruction so that it is marked as having side effects to match the definition of CSRRS and the RV64 instruction. And we don't need to explicitly clear mayLoad/mayStore since those can be inferred now. Differential Revision: https://reviews.llvm.org/D92786 Added: Modified: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 65395706a40a..e4ffb42eca28 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -143,13 +143,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { } break; } - case RISCVISD::READ_CYCLE_WIDE: - assert(!Subtarget->is64Bit() && "READ_CYCLE_WIDE is only used on riscv32"); - - ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ReadCycleWide, DL, MVT::i32, - MVT::i32, MVT::Other, - Node->getOperand(0))); - return; } // Select the default instruction. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index f6eec9e0f870..768dd8a636fe 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -25,6 +25,8 @@ def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>; def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, SDTCisSameAs<0, 4>, SDTCisSameAs<4, 5>]>; +def SDT_RISCVReadCycleWide : SDTypeProfile<2, 0, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>]>; // Target-independent nodes, but with target-specific formats. def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, @@ -52,6 +54,10 @@ def riscv_sllw : SDNode<"RISCVISD::SLLW", SDTIntShiftOp>; def riscv_sraw : SDNode<"RISCVISD::SRAW", SDTIntShiftOp>; def riscv_srlw : SDNode<"RISCVISD::SRLW", SDTIntShiftOp>; +def riscv_read_cycle_wide : SDNode<"RISCVISD::READ_CYCLE_WIDE", + SDT_RISCVReadCycleWide, + [SDNPHasChain, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// @@ -1170,9 +1176,10 @@ let Predicates = [IsRV64] in def : Pat<(readcyclecounter), (CSRRS CYCLE.Encoding, X0)>; // On RV32, ReadCycleWide will be expanded to the suggested loop reading both // halves of the 64-bit "cycle" CSR. -let Predicates = [IsRV32], usesCustomInserter = 1, hasSideEffects = 0, -mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in -def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">; +let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in +def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), + [(set GPR:$lo, GPR:$hi, (riscv_read_cycle_wide))], + "", "">; /// traps _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
