Author: Craig Topper Date: 2020-12-04T10:34:12-08:00 New Revision: ad923edfc1ce0c0b60e8270954c8d098aab3c3f8
URL: https://github.com/llvm/llvm-project/commit/ad923edfc1ce0c0b60e8270954c8d098aab3c3f8 DIFF: https://github.com/llvm/llvm-project/commit/ad923edfc1ce0c0b60e8270954c8d098aab3c3f8.diff LOG: [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591 It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name? Differential Revision: https://reviews.llvm.org/D92147 Added: Modified: lld/test/ELF/riscv-branch.s lld/test/ELF/riscv-jal.s lld/test/ELF/riscv-undefined-weak.s llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVInstrInfoC.td llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h llvm/test/CodeGen/RISCV/compress.ll llvm/test/MC/Disassembler/RISCV/branch-targets.txt llvm/test/MC/RISCV/compress-cjal.s llvm/test/MC/RISCV/compress-rv32i.s llvm/test/MC/RISCV/fixups-compressed.s llvm/test/MC/RISCV/fixups.s llvm/test/MC/RISCV/rv32-relaxation.s llvm/test/MC/RISCV/rv32c-only-valid.s llvm/test/MC/RISCV/rv32c-valid.s llvm/test/MC/RISCV/rv32e-valid.s llvm/test/MC/RISCV/rv32i-valid.s llvm/test/MC/RISCV/rv64-relax-all.s llvm/test/MC/RISCV/rv64-relaxation.s llvm/test/MC/RISCV/rvi-aliases-valid.s llvm/test/MC/RISCV/rvv/snippet.s Removed: ################################################################################ diff --git a/lld/test/ELF/riscv-branch.s b/lld/test/ELF/riscv-branch.s index af6fd31d7726..3760e31c6d83 100644 --- a/lld/test/ELF/riscv-branch.s +++ b/lld/test/ELF/riscv-branch.s @@ -5,17 +5,21 @@ # RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32 # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64 -# RUN: llvm-objdump -d %t.rv32 | FileCheck %s -# RUN: llvm-objdump -d %t.rv64 | FileCheck %s -# CHECK: 63 02 00 00 beqz zero, 4 -# CHECK: e3 1e 00 fe bnez zero, -4 +# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32 +# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64 +# CHECK-32: 63 02 00 00 beqz zero, 0x110b8 +# CHECK-32: e3 1e 00 fe bnez zero, 0x110b4 +# CHECK-64: 63 02 00 00 beqz zero, 0x11124 +# CHECK-64: e3 1e 00 fe bnez zero, 0x11120 # # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits -# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s -# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s -# LIMITS: e3 0f 00 7e beqz zero, 4094 -# LIMITS-NEXT: 63 10 00 80 bnez zero, -4096 +# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s +# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s +# LIMITS-32: e3 0f 00 7e beqz zero, 0x120b2 +# LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8 +# LIMITS-64: e3 0f 00 7e beqz zero, 0x1211e +# LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s diff --git a/lld/test/ELF/riscv-jal.s b/lld/test/ELF/riscv-jal.s index 63c716bbf3fe..97a03cc2f9b7 100644 --- a/lld/test/ELF/riscv-jal.s +++ b/lld/test/ELF/riscv-jal.s @@ -5,17 +5,21 @@ # RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32 # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64 -# RUN: llvm-objdump -d %t.rv32 | FileCheck %s -# RUN: llvm-objdump -d %t.rv64 | FileCheck %s -# CHECK: 6f 00 40 00 j 4 -# CHECK: ef f0 df ff jal -4 +# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32 +# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64 +# CHECK-32: 6f 00 40 00 j 0x110b8 +# CHECK-32: ef f0 df ff jal 0x110b4 +# CHECK-64: 6f 00 40 00 j 0x11124 +# CHECK-64: ef f0 df ff jal 0x11120 # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits -# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s -# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s -# LIMITS: 6f f0 ff 7f j 1048574 -# LIMITS-NEXT: ef 00 00 80 jal -1048576 +# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s +# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s +# LIMITS-32: 6f f0 ff 7f j 0x1110b2 +# LIMITS-32-NEXT: ef 00 00 80 jal 0xfff110b8 +# LIMITS-64: 6f f0 ff 7f j 0x11111e +# LIMITS-64-NEXT: ef 00 00 80 jal 0xfffffffffff11124 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s diff --git a/lld/test/ELF/riscv-undefined-weak.s b/lld/test/ELF/riscv-undefined-weak.s index acc5693cd5f9..caa5637d18f2 100644 --- a/lld/test/ELF/riscv-undefined-weak.s +++ b/lld/test/ELF/riscv-undefined-weak.s @@ -52,15 +52,14 @@ relative: # PC-LABEL: <branch>: # PC-NEXT: auipc ra, 1048559 # PC-NEXT: jalr -368(ra) -## FIXME: llvm-objdump -d should print the address, instead of the offset. -# PC-NEXT: j -70008 +# PC-NEXT: j 0x0 ## If .dynsym exists, an undefined weak symbol is preemptible. ## We create a PLT entry and redirect the reference to it. # PLT-LABEL: <branch>: # PLT-NEXT: auipc ra, 0 # PLT-NEXT: jalr 56(ra) -# PLT-NEXT: j -70448 +# PLT-NEXT: j 0x0 branch: call target jal x0, target diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 2c7038a0a8ac..56568dfcecba 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -102,6 +102,24 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, MO.getExpr()->print(O, &MAI); } +void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, + unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + if (!MO.isImm()) + return printOperand(MI, OpNo, STI, O); + + if (PrintBranchImmAsAddress) { + uint64_t Target = Address + MO.getImm(); + if (!STI.hasFeature(RISCV::Feature64Bit)) + Target &= 0xffffffff; + O << formatHex(Target); + } else { + O << MO.getImm(); + } +} + void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index 70ec0fe2a0cc..ddffcbe343d7 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -32,6 +32,8 @@ class RISCVInstPrinter : public MCInstPrinter { void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); + void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFenceArg(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 442c8be841b3..f79ab1ab1d7f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -604,15 +604,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_SIMM12: Ok = isInt<12>(Imm); break; - case RISCVOp::OPERAND_SIMM13_LSB0: - Ok = isShiftedInt<12, 1>(Imm); - break; case RISCVOp::OPERAND_UIMM20: Ok = isUInt<20>(Imm); break; - case RISCVOp::OPERAND_SIMM21_LSB0: - Ok = isShiftedInt<20, 1>(Imm); - break; case RISCVOp::OPERAND_UIMMLOG2XLEN: if (STI.getTargetTriple().isArch64Bit()) Ok = isUInt<6>(Imm); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 5733e5e21f67..f6eec9e0f870 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -160,6 +160,7 @@ def simm12_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT, // A 13-bit signed immediate where the least significant bit is zero. def simm13_lsb0 : Operand<OtherVT> { let ParserMatchClass = SImmAsmOperand<13, "Lsb0">; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<13>"; let MCOperandPredicate = [{ @@ -168,8 +169,7 @@ def simm13_lsb0 : Operand<OtherVT> { return isShiftedInt<12, 1>(Imm); return MCOp.isBareSymbolRef(); }]; - let OperandType = "OPERAND_SIMM13_LSB0"; - let OperandNamespace = "RISCVOp"; + let OperandType = "OPERAND_PCREL"; } class UImm20Operand : Operand<XLenVT> { @@ -199,6 +199,7 @@ def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> { // A 21-bit signed immediate where the least significant bit is zero. def simm21_lsb0_jal : Operand<OtherVT> { let ParserMatchClass = Simm21Lsb0JALAsmOperand; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<21>"; let MCOperandPredicate = [{ @@ -207,8 +208,7 @@ def simm21_lsb0_jal : Operand<OtherVT> { return isShiftedInt<20, 1>(Imm); return MCOp.isBareSymbolRef(); }]; - let OperandType = "OPERAND_SIMM21_LSB0"; - let OperandNamespace = "RISCVOp"; + let OperandType = "OPERAND_PCREL"; } def BareSymbol : AsmOperandClass { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index fbddde2b4bdc..672dd3fcbbc3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -140,6 +140,7 @@ def uimm8_lsb000 : Operand<XLenVT>, def simm9_lsb0 : Operand<OtherVT>, ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> { let ParserMatchClass = SImmAsmOperand<9, "Lsb0">; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<9>"; let MCOperandPredicate = [{ @@ -149,6 +150,7 @@ def simm9_lsb0 : Operand<OtherVT>, return MCOp.isBareSymbolRef(); }]; + let OperandType = "OPERAND_PCREL"; } // A 9-bit unsigned immediate where the least significant three bits are zero. @@ -200,6 +202,7 @@ def simm10_lsb0000nonzero : Operand<XLenVT>, def simm12_lsb0 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> { let ParserMatchClass = SImmAsmOperand<12, "Lsb0">; + let PrintMethod = "printBranchOperand"; let EncoderMethod = "getImmOpValueAsr1"; let DecoderMethod = "decodeSImmOperandAndLsl1<12>"; let MCOperandPredicate = [{ @@ -208,6 +211,7 @@ def simm12_lsb0 : Operand<XLenVT>, return isShiftedInt<11, 1>(Imm); return MCOp.isBareSymbolRef(); }]; + let OperandType = "OPERAND_PCREL"; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h index 3043cd777dc2..db036e18a286 100644 --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -132,9 +132,7 @@ enum OperandType : unsigned { OPERAND_UIMM5, OPERAND_UIMM12, OPERAND_SIMM12, - OPERAND_SIMM13_LSB0, OPERAND_UIMM20, - OPERAND_SIMM21_LSB0, OPERAND_UIMMLOG2XLEN, OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN }; diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll index 21547e671e9b..8095d2a76b28 100644 --- a/llvm/test/CodeGen/RISCV/compress.ll +++ b/llvm/test/CodeGen/RISCV/compress.ll @@ -50,34 +50,34 @@ define i32 @simple_arith(i32 %a, i32 %b) #0 { define i32 @select(i32 %a, i32 *%b) #0 { ; RV32IC-LABEL: <select>: ; RV32IC: c.lw a2, 0(a1) -; RV32IC-NEXT: c.beqz a2, 4 +; RV32IC-NEXT: c.beqz a2, 0x18 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: c.bnez a2, 4 +; RV32IC-NEXT: c.bnez a2, 0x1e ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bltu a2, a0, 6 +; RV32IC-NEXT: bltu a2, a0, 0x26 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bgeu a0, a2, 6 +; RV32IC-NEXT: bgeu a0, a2, 0x2e ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bltu a0, a2, 6 +; RV32IC-NEXT: bltu a0, a2, 0x36 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bgeu a2, a0, 6 +; RV32IC-NEXT: bgeu a2, a0, 0x3e ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: blt a2, a0, 6 +; RV32IC-NEXT: blt a2, a0, 0x46 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: bge a0, a2, 6 +; RV32IC-NEXT: bge a0, a2, 0x4e ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a2, 0(a1) -; RV32IC-NEXT: blt a0, a2, 6 +; RV32IC-NEXT: blt a0, a2, 0x56 ; RV32IC-NEXT: c.mv a0, a2 ; RV32IC-NEXT: c.lw a1, 0(a1) -; RV32IC-NEXT: bge a1, a0, 6 +; RV32IC-NEXT: bge a1, a0, 0x5e ; RV32IC-NEXT: c.mv a0, a1 ; RV32IC-NEXT: c.jr ra %val1 = load volatile i32, i32* %b diff --git a/llvm/test/MC/Disassembler/RISCV/branch-targets.txt b/llvm/test/MC/Disassembler/RISCV/branch-targets.txt index d3486d2b99f9..4cb451904c38 100644 --- a/llvm/test/MC/Disassembler/RISCV/branch-targets.txt +++ b/llvm/test/MC/Disassembler/RISCV/branch-targets.txt @@ -15,13 +15,13 @@ label1: bnez a0, label1 bnez a0, label2 # CHECK-LABEL: <label1>: -# CHECK-NEXT: jal zero, 0 <label1> -# CHECK-NEXT: jal zero, 20 <label2> -# CHECK-NEXT: bne a0, zero, -8 <label1> -# CHECK-NEXT: bne a0, zero, 12 <label2> -# CHECK-NEXT: c.j -16 <label1> -# CHECK-NEXT: c.j 6 <label2> -# CHECK-NEXT: c.bnez a0, -20 <label1> -# CHECK-NEXT: c.bnez a0, 2 <label2> +# CHECK-NEXT: jal zero, 0x0 <label1> +# CHECK-NEXT: jal zero, 0x18 <label2> +# CHECK-NEXT: bne a0, zero, 0x0 <label1> +# CHECK-NEXT: bne a0, zero, 0x18 <label2> +# CHECK-NEXT: c.j 0x0 <label1> +# CHECK-NEXT: c.j 0x18 <label2> +# CHECK-NEXT: c.bnez a0, 0x0 <label1> +# CHECK-NEXT: c.bnez a0, 0x18 <label2> label2: diff --git a/llvm/test/MC/RISCV/compress-cjal.s b/llvm/test/MC/RISCV/compress-cjal.s index 9e9cc52693df..7a3af3f6de90 100644 --- a/llvm/test/MC/RISCV/compress-cjal.s +++ b/llvm/test/MC/RISCV/compress-cjal.s @@ -4,14 +4,16 @@ # RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \ -# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIASOBJ %s # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \ -# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INSTOBJ %s # c.jal is an rv32 only instruction. jal ra, 2046 # CHECK-BYTES: fd 2f +# CHECK-ALIASOBJ: jal 0x7fe # CHECK-ALIAS: jal 2046 # CHECK-INST: c.jal 2046 +# CHECK-INSTOBJ: c.jal 0x7fe # CHECK: # encoding: [0xfd,0x2f] diff --git a/llvm/test/MC/RISCV/compress-rv32i.s b/llvm/test/MC/RISCV/compress-rv32i.s index 886b580db69c..c6cd92954428 100644 --- a/llvm/test/MC/RISCV/compress-rv32i.s +++ b/llvm/test/MC/RISCV/compress-rv32i.s @@ -1,24 +1,24 @@ # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS,CHECK-ALIASASM %s # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \ -# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-INSTASM %s # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d - \ -# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIASOBJ32 %s # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv32 --mattr=+c -d -M no-aliases - \ -# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ32 %s # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \ -# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-ALIAS,CHECK-ALIASASM %s # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \ -# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s +# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST,CHECK-INSTASM %s # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d - \ -# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIASOBJ64 %s # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv64 --mattr=+c -d -M no-aliases - \ -# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ64 %s # CHECK-BYTES: 2e 85 # CHECK-ALIAS: add a0, zero, a1 @@ -135,20 +135,32 @@ and s0, s0, a5 and s0, a5, s0 # CHECK-BYTES: 01 b0 -# CHECK-ALIAS: j -2048 -# CHECK-INST: c.j -2048 +# CHECK-ALIASASM: j -2048 +# CHECK-ALIASOBJ32: j 0xfffff826 +# CHECK-ALIASOBJ64: j 0xfffffffffffff826 +# CHECK-INSTASM: c.j -2048 +# CHECK-INSTOBJ32: c.j 0xfffff826 +# CHECK-INSTOBJ64: c.j 0xfffffffffffff826 # CHECK: # encoding: [0x01,0xb0] jal zero, -2048 # CHECK-BYTES: 01 d0 -# CHECK-ALIAS: beqz s0, -256 -# CHECK-INST: c.beqz s0, -256 +# CHECK-ALIASASM: beqz s0, -256 +# CHECK-ALIASOBJ32: beqz s0, 0xffffff28 +# CHECK-ALIASOBJ64: beqz s0, 0xffffffffffffff28 +# CHECK-INSTASM: c.beqz s0, -256 +# CHECK-INSTOBJ32: c.beqz s0, 0xffffff28 +# CHECK-INSTOBJ64: c.beqz s0, 0xffffffffffffff28 # CHECK: # encoding: [0x01,0xd0] beq s0, zero, -256 # CHECK-BYTES: 7d ec -# CHECk-ALIAS: bnez s0, 254 -# CHECK-INST: c.bnez s0, 254 +# CHECK-ALIASASM: bnez s0, 254 +# CHECK-ALIASOBJ32: bnez s0, 0x128 +# CHECK-ALIASOBJ64: bnez s0, 0x128 +# CHECK-INSTASM: c.bnez s0, 254 +# CHECK-INSTOBJ32: c.bnez s0, 0x128 +# CHECK-INSTOBJ64: c.bnez s0, 0x128 # CHECK: # encoding: [0x7d,0xec] bne s0, zero, 254 diff --git a/llvm/test/MC/RISCV/fixups-compressed.s b/llvm/test/MC/RISCV/fixups-compressed.s index 3c5fcffb567c..e856fd8a1794 100644 --- a/llvm/test/MC/RISCV/fixups-compressed.s +++ b/llvm/test/MC/RISCV/fixups-compressed.s @@ -10,13 +10,13 @@ # CHECK-INSTR: c.j 0 c.j .LBB0_2 # CHECK: fixup A - offset: 0, value: func1, kind: fixup_riscv_rvc_jump -# CHECK-INSTR: c.jal 6 +# CHECK-INSTR: c.jal 0x8 c.jal func1 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch -# CHECK-INSTR: c.beqz a3, -4 +# CHECK-INSTR: c.beqz a3, 0x0 c.beqz a3, .LBB0_2 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch -# CHECK-INSTR: c.bnez a5, -6 +# CHECK-INSTR: c.bnez a5, 0x0 c.bnez a5, .LBB0_2 func1: diff --git a/llvm/test/MC/RISCV/fixups.s b/llvm/test/MC/RISCV/fixups.s index 45d46d84be9a..ccfbb2512ab4 100644 --- a/llvm/test/MC/RISCV/fixups.s +++ b/llvm/test/MC/RISCV/fixups.s @@ -37,16 +37,16 @@ sw t1, %pcrel_lo(1b)(t1) jal zero, .LBB0 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_jal -# CHECK-INSTR: jal zero, -28 +# CHECK-INSTR: jal zero, 0x0 jal zero, .LBB2 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB2, kind: fixup_riscv_jal -# CHECK-INSTR: jal zero, 330996 +# CHECK-INSTR: jal zero, 0x50d14 beq a0, a1, .LBB0 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_branch -# CHECK-INSTR: beq a0, a1, -36 +# CHECK-INSTR: beq a0, a1, 0x0 blt a0, a1, .LBB1 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB1, kind: fixup_riscv_branch -# CHECK-INSTR: blt a0, a1, 1108 +# CHECK-INSTR: blt a0, a1, 0x47c .fill 1104 diff --git a/llvm/test/MC/RISCV/rv32-relaxation.s b/llvm/test/MC/RISCV/rv32-relaxation.s index 609fa7c83e84..1a5da352aa2b 100644 --- a/llvm/test/MC/RISCV/rv32-relaxation.s +++ b/llvm/test/MC/RISCV/rv32-relaxation.s @@ -18,102 +18,102 @@ NEAR_NEGATIVE: start: c.bnez a0, NEAR -#INSTR: c.bnez a0, 72 +#INSTR: c.bnez a0, 0x91e #RELAX-INSTR: c.bnez a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.bnez a0, NEAR_NEGATIVE -#INSTR: c.bnez a0, -4 +#INSTR: c.bnez a0, 0x8d4 #RELAX-INSTR: c.bnez a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.bnez a0, FAR_BRANCH -#INSTR-NEXT: bne a0, zero, 326 +#INSTR-NEXT: bne a0, zero, 0xa20 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.bnez a0, FAR_BRANCH_NEGATIVE -#INSTR-NEXT: bne a0, zero, -268 +#INSTR-NEXT: bne a0, zero, 0x7d2 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.bnez a0, FAR_JUMP -#INSTR-NEXT: bne a0, zero, 2320 +#INSTR-NEXT: bne a0, zero, 0x11f2 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.bnez a0, FAR_JUMP_NEGATIVE -#INSTR-NEXT: bne a0, zero, -2278 +#INSTR-NEXT: bne a0, zero, 0x0 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, NEAR -#INSTR-NEXT: c.beqz a0, 52 +#INSTR-NEXT: c.beqz a0, 0x91e #RELAX-INSTR-NEXT: c.beqz a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.beqz a0, NEAR_NEGATIVE -#INSTR-NEXT: c.beqz a0, -24 +#INSTR-NEXT: c.beqz a0, 0x8d4 #RELAX-INSTR-NEXT: c.beqz a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.beqz a0, FAR_BRANCH -#INSTR-NEXT: beq a0, zero, 306 +#INSTR-NEXT: beq a0, zero, 0xa20 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, FAR_BRANCH_NEGATIVE -#INSTR-NEXT: beq a0, zero, -288 +#INSTR-NEXT: beq a0, zero, 0x7d2 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, FAR_JUMP -#INSTR-NEXT: beq a0, zero, 2300 +#INSTR-NEXT: beq a0, zero, 0x11f2 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, FAR_JUMP_NEGATIVE -#INSTR-NEXT: beq a0, zero, -2298 +#INSTR-NEXT: beq a0, zero, 0x0 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.j NEAR -#INSTR-NEXT: c.j 32 +#INSTR-NEXT: c.j 0x91e #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j NEAR_NEGATIVE -#INSTR-NEXT: c.j -44 +#INSTR-NEXT: c.j 0x8d4 #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j FAR_BRANCH -#INSTR-NEXT: c.j 286 +#INSTR-NEXT: c.j 0xa20 #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j FAR_BRANCH_NEGATIVE -#INSTR-NEXT: c.j -306 +#INSTR-NEXT: c.j 0x7d2 #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j FAR_JUMP -#INSTR-NEXT: jal zero, 2284 +#INSTR-NEXT: jal zero, 0x11f2 #RELAX-INSTR-NEXT: jal zero, 0 #RELAX-RELOC: R_RISCV_JAL c.j FAR_JUMP_NEGATIVE -#INSTR-NEXT: jal zero, -2314 +#INSTR-NEXT: jal zero, 0x0 #RELAX-INSTR-NEXT: jal zero, 0 #RELAX-RELOC: R_RISCV_JAL c.jal NEAR -#INSTR: c.jal 16 +#INSTR: c.jal 0x91e #RELAX-INSTR: c.jal 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.jal NEAR_NEGATIVE -#INSTR: c.jal -60 +#INSTR: c.jal 0x8d4 #RELAX-INSTR: c.jal 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.jal FAR_BRANCH -#INSTR-NEXT: c.jal 270 +#INSTR-NEXT: c.jal 0xa20 #RELAX-INSTR-NEXT: c.jal 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.jal FAR_BRANCH_NEGATIVE -#INSTR-NEXT: c.jal -322 +#INSTR-NEXT: c.jal 0x7d2 #RELAX-INSTR-NEXT: c.jal 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.jal FAR_JUMP -#INSTR-NEXT: jal ra, 2268 +#INSTR-NEXT: jal ra, 0x11f2 #RELAX-INSTR-NEXT: jal ra, 0 #RELAX-RELOC: R_RISCV_JAL c.jal FAR_JUMP_NEGATIVE -#INSTR-NEXT: jal ra, -2330 +#INSTR-NEXT: jal ra, 0x0 #RELAX-INSTR-NEXT: jal ra, 0 #RELAX-RELOC: R_RISCV_JAL diff --git a/llvm/test/MC/RISCV/rv32c-only-valid.s b/llvm/test/MC/RISCV/rv32c-only-valid.s index b04e7b4d3971..edd5a656eeae 100644 --- a/llvm/test/MC/RISCV/rv32c-only-valid.s +++ b/llvm/test/MC/RISCV/rv32c-only-valid.s @@ -2,7 +2,7 @@ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \ # RUN: | llvm-objdump --mattr=+c -M no-aliases -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv32 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ @@ -14,7 +14,8 @@ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-RV32-AND-EXT %s -# CHECK-ASM-AND-OBJ: c.jal 2046 +# CHECK-OBJ: c.jal 0x7fe +# CHECK-ASM: c.jal 2046 # CHECK-ASM: encoding: [0xfd,0x2f] # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) # CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s index 8b3108f1f857..07c935f0721a 100644 --- a/llvm/test/MC/RISCV/rv32c-valid.s +++ b/llvm/test/MC/RISCV/rv32c-valid.s @@ -2,7 +2,7 @@ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \ # RUN: | llvm-objdump --mattr=+c -M no-aliases -d -r - \ -# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \ @@ -24,7 +24,8 @@ c.lw a2, 0(a0) # CHECK-ASM: encoding: [0xfc,0xde] c.sw a5, 124(a3) -# CHECK-ASM-AND-OBJ: c.j -2048 +# CHECK-OBJ: c.j 0xfffff808 +# CHECK-ASM: c.j -2048 # CHECK-ASM: encoding: [0x01,0xb0] c.j -2048 # CHECK-ASM-AND-OBJ: c.jr a7 @@ -33,10 +34,12 @@ c.jr a7 # CHECK-ASM-AND-OBJ: c.jalr a1 # CHECK-ASM: encoding: [0x82,0x95] c.jalr a1 -# CHECK-ASM-AND-OBJ: c.beqz a3, -256 +# CHECK-OBJ: c.beqz a3, 0xffffff0e +# CHECK-ASM: c.beqz a3, -256 # CHECK-ASM: encoding: [0x81,0xd2] c.beqz a3, -256 -# CHECK-ASM-AND-OBJ: c.bnez a5, 254 +# CHECK-OBJ: c.bnez a5, 0x10e +# CHECK-ASM: c.bnez a5, 254 # CHECK-ASM: encoding: [0xfd,0xef] c.bnez a5, 254 diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s index 128e42bdd21a..7befe83f72e1 100644 --- a/llvm/test/MC/RISCV/rv32e-valid.s +++ b/llvm/test/MC/RISCV/rv32e-valid.s @@ -1,8 +1,8 @@ # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \ -# RUN: | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \ # RUN: | llvm-objdump -M no-aliases -d -r - \ -# RUN: | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # This file provides a basic sanity check for RV32E, checking that the expected # set of registers and instructions are accepted. @@ -12,20 +12,26 @@ lui x0, 1 # CHECK-ASM-AND-OBJ: auipc ra, 2 auipc x1, 2 -# CHECK-ASM-AND-OBJ: jal sp, 4 +# CHECK-OBJ: jal sp, 0xc +# CHECK-ASM: jal sp, 4 jal x2, 4 # CHECK-ASM-AND-OBJ: jalr gp, 4(gp) jalr x3, x3, 4 -# CHECK-ASM-AND-OBJ: beq tp, t0, 8 +# CHECK-OBJ: beq tp, t0, 0x18 +# CHECK-ASM: beq tp, t0, 8 beq x4, x5, 8 -# CHECK-ASM-AND-OBJ: bne t1, t2, 12 +# CHECK-OBJ: bne t1, t2, 0x20 +# CHECK-ASM: bne t1, t2, 12 bne x6, x7, 12 -# CHECK-ASM-AND-OBJ: blt s0, s1, 16 +# CHECK-OBJ: blt s0, s1, 0x28 +# CHECK-ASM: blt s0, s1, 16 blt x8, x9, 16 -# CHECK-ASM-AND-OBJ: bge a0, a1, 20 +# CHECK-OBJ: bge a0, a1, 0x30 +# CHECK-ASM: bge a0, a1, 20 bge x10, x11, 20 -# CHECK-ASM-AND-OBJ: bgeu a2, a3, 24 +# CHECK-OBJ: bgeu a2, a3, 0x38 +# CHECK-ASM: bgeu a2, a3, 24 bgeu x12, x13, 24 # CHECK-ASM-AND-OBJ: lb a4, 25(a5) diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s index 580f0f548c3f..64883e8b5ba6 100644 --- a/llvm/test/MC/RISCV/rv32i-valid.s +++ b/llvm/test/MC/RISCV/rv32i-valid.s @@ -4,10 +4,10 @@ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \ # RUN: | llvm-objdump -M no-aliases -d -r - \ -# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ32,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \ # RUN: | llvm-objdump -M no-aliases -d -r - \ -# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ64,CHECK-ASM-AND-OBJ %s .equ CONST, 30 @@ -68,10 +68,12 @@ auipc a0, %pcrel_hi(foo) # CHECK-ASM: encoding: [0x17,0xe5,0x01,0x00] auipc a0, CONST -# CHECK-ASM-AND-OBJ: jal a2, 1048574 +# CHECK-OBJ: jal a2, 0x100042 +# CHECK-ASM: jal a2, 1048574 # CHECK-ASM: encoding: [0x6f,0xf6,0xff,0x7f] jal a2, 1048574 -# CHECK-ASM-AND-OBJ: jal a3, 256 +# CHECK-OBJ: jal a3, 0x148 +# CHECK-ASM: jal a3, 256 # CHECK-ASM: encoding: [0xef,0x06,0x00,0x10] jal a3, 256 # CHECK-ASM: jal a0, foo @@ -84,13 +86,15 @@ jal a0, foo # CHECK-OBJ: jal a0, 0 # CHECK-OBJ: R_RISCV_JAL a0 jal a0, a0 -# CHECK-ASM-AND-OBJ: jal a0, 30 +# CHECK-OBJ: jal a0, 0x72 +# CHECK-ASM: jal a0, 30 # CHECK-ASM: encoding: [0x6f,0x05,0xe0,0x01] jal a0, CONST # CHECK-ASM-AND-OBJ: jal s0, 0 # CHECK-ASM: encoding: [0x6f,0x04,0x00,0x00] jal s0, (0) -# CHECK-ASM-AND-OBJ: jal s0, 156 +# CHECK-OBJ: jal s0, 0xf8 +# CHECK-ASM: jal s0, 156 # CHECK-ASM: encoding: [0x6f,0x04,0xc0,0x09] jal s0, (0xff-99) # CHECK-ASM: encoding: [0x6f,0bAAAA0000,A,A] @@ -113,25 +117,33 @@ jalr sp, zero, 256 # CHECK-ASM: encoding: [0xe7,0x05,0xe6,0x01] jalr a1, CONST(a2) -# CHECK-ASM-AND-OBJ: beq s1, s1, 102 +# CHECK-OBJ: beq s1, s1, 0xde +# CHECK-ASM: beq s1, s1, 102 # CHECK-ASM: encoding: [0x63,0x83,0x94,0x06] beq s1, s1, 102 -# CHECK-ASM-AND-OBJ: bne a4, a5, -4096 +# CHECK-OBJ32: bne a4, a5, 0xfffff07c +# CHECK-OBJ64: bne a4, a5, 0xfffffffffffff07c +# CHECK-ASM: bne a4, a5, -4096 # CHECK-ASM: encoding: [0x63,0x10,0xf7,0x80] bne a4, a5, -4096 -# CHECK-ASM-AND-OBJ: blt sp, gp, 4094 +# CHECK-OBJ: blt sp, gp, 0x107e +# CHECK-ASM: blt sp, gp, 4094 # CHECK-ASM: encoding: [0xe3,0x4f,0x31,0x7e] blt sp, gp, 4094 -# CHECK-ASM-AND-OBJ: bge s2, ra, -224 +# CHECK-OBJ32: bge s2, ra, 0xffffffa4 +# CHECK-OBJ64: bge s2, ra, 0xffffffffffffffa4 +# CHECK-ASM: bge s2, ra, -224 # CHECK-ASM: encoding: [0xe3,0x50,0x19,0xf2] bge s2, ra, -224 # CHECK-ASM-AND-OBJ: bltu zero, zero, 0 # CHECK-ASM: encoding: [0x63,0x60,0x00,0x00] bltu zero, zero, 0 -# CHECK-ASM-AND-OBJ: bgeu s8, sp, 512 +# CHECK-OBJ: bgeu s8, sp, 0x28c +# CHECK-ASM: bgeu s8, sp, 512 # CHECK-ASM: encoding: [0x63,0x70,0x2c,0x20] bgeu s8, sp, 512 -# CHECK-ASM-AND-OBJ: bgeu t0, t1, 30 +# CHECK-OBJ: bgeu t0, t1, 0xae +# CHECK-ASM: bgeu t0, t1, 30 # CHECK-ASM: encoding: [0x63,0xff,0x62,0x00] bgeu t0, t1, CONST diff --git a/llvm/test/MC/RISCV/rv64-relax-all.s b/llvm/test/MC/RISCV/rv64-relax-all.s index 5d6d74b882c1..84ef373b741b 100644 --- a/llvm/test/MC/RISCV/rv64-relax-all.s +++ b/llvm/test/MC/RISCV/rv64-relax-all.s @@ -6,10 +6,10 @@ NEAR: -# INSTR: c.beqz a0, 0 <NEAR> -# RELAX-INSTR: beq a0, zero, 0 <NEAR> +# INSTR: c.beqz a0, 0x0 <NEAR> +# RELAX-INSTR: beq a0, zero, 0x0 <NEAR> c.beqz a0, NEAR -# INSTR: c.j -2 <NEAR> -# RELAX-INSTR: jal zero, -4 <NEAR> +# INSTR: c.j 0x0 <NEAR> +# RELAX-INSTR: jal zero, 0x0 <NEAR> c.j NEAR diff --git a/llvm/test/MC/RISCV/rv64-relaxation.s b/llvm/test/MC/RISCV/rv64-relaxation.s index 0e057e36afbf..e71cf20a6413 100644 --- a/llvm/test/MC/RISCV/rv64-relaxation.s +++ b/llvm/test/MC/RISCV/rv64-relaxation.s @@ -18,77 +18,77 @@ NEAR_NEGATIVE: start: c.bnez a0, NEAR -#INSTR: c.bnez a0, 56 +#INSTR: c.bnez a0, 0x90e #RELAX-INSTR: c.bnez a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.bnez a0, NEAR_NEGATIVE -#INSTR: c.bnez a0, -4 +#INSTR: c.bnez a0, 0x8d4 #RELAX-INSTR: c.bnez a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.bnez a0, FAR_BRANCH -#INSTR-NEXT: bne a0, zero, 310 +#INSTR-NEXT: bne a0, zero, 0xa10 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.bnez a0, FAR_BRANCH_NEGATIVE -#INSTR-NEXT: bne a0, zero, -268 +#INSTR-NEXT: bne a0, zero, 0x7d2 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.bnez a0, FAR_JUMP -#INSTR-NEXT: bne a0, zero, 2304 +#INSTR-NEXT: bne a0, zero, 0x11e2 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.bnez a0, FAR_JUMP_NEGATIVE -#INSTR-NEXT: bne a0, zero, -2278 +#INSTR-NEXT: bne a0, zero, 0x0 #RELAX-INSTR-NEXT: bne a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, NEAR -#INSTR-NEXT: c.beqz a0, 36 +#INSTR-NEXT: c.beqz a0, 0x90e #RELAX-INSTR-NEXT: c.beqz a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.beqz a0, NEAR_NEGATIVE -#INSTR-NEXT: c.beqz a0, -24 +#INSTR-NEXT: c.beqz a0, 0x8d4 #RELAX-INSTR-NEXT: c.beqz a0, 0 #RELAX-RELOC: R_RISCV_RVC_BRANCH c.beqz a0, FAR_BRANCH -#INSTR-NEXT: beq a0, zero, 290 +#INSTR-NEXT: beq a0, zero, 0xa10 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, FAR_BRANCH_NEGATIVE -#INSTR-NEXT: beq a0, zero, -288 +#INSTR-NEXT: beq a0, zero, 0x7d2 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, FAR_JUMP -#INSTR-NEXT: beq a0, zero, 2284 +#INSTR-NEXT: beq a0, zero, 0x11e2 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.beqz a0, FAR_JUMP_NEGATIVE -#INSTR-NEXT: beq a0, zero, -2298 +#INSTR-NEXT: beq a0, zero, 0x0 #RELAX-INSTR-NEXT: beq a0, zero, 0 #RELAX-RELOC: R_RISCV_BRANCH c.j NEAR -#INSTR-NEXT: c.j 16 +#INSTR-NEXT: c.j 0x90e #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j NEAR_NEGATIVE -#INSTR-NEXT: c.j -44 +#INSTR-NEXT: c.j 0x8d4 #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j FAR_BRANCH -#INSTR-NEXT: c.j 270 +#INSTR-NEXT: c.j 0xa10 #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j FAR_BRANCH_NEGATIVE -#INSTR-NEXT: c.j -306 +#INSTR-NEXT: c.j 0x7d2 #RELAX-INSTR-NEXT: c.j 0 #RELAX-RELOC: R_RISCV_RVC_JUMP c.j FAR_JUMP -#INSTR-NEXT: jal zero, 2268 +#INSTR-NEXT: jal zero, 0x11e2 #RELAX-INSTR-NEXT: jal zero, 0 #RELAX-RELOC: R_RISCV_JAL c.j FAR_JUMP_NEGATIVE -#INSTR-NEXT: jal zero, -2314 +#INSTR-NEXT: jal zero, 0x0 #RELAX-INSTR-NEXT: jal zero, 0 #RELAX-RELOC: R_RISCV_JAL diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s index a78efd48fb3d..af5c08a8b581 100644 --- a/llvm/test/MC/RISCV/rvi-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -69,41 +69,63 @@ sgt x1, x2, x3 # CHECK-S-OBJ: sltu tp, t1, t0 sgtu x4, x5, x6 -# CHECK-S-OBJ-NOALIAS: beq a0, zero, 512 -# CHECK-S-OBJ: beqz a0, 512 +# CHECK-S-NOALIAS: beq a0, zero, 512 +# CHECK-S: beqz a0, 512 +# CHECK-OBJ-NOALIAS: beq a0, zero, 0x22c +# CHECK-OBJ: beqz a0, 0x22c beqz x10, 512 -# CHECK-S-OBJ-NOALIAS: bne a1, zero, 1024 -# CHECK-S-OBJ: bnez a1, 1024 +# CHECK-S-NOALIAS: bne a1, zero, 1024 +# CHECK-S: bnez a1, 1024 +# CHECK-OBJ-NOALIAS: bne a1, zero, 0x430 +# CHECK-OBJ: bnez a1, 0x430 bnez x11, 1024 -# CHECK-S-OBJ-NOALIAS: bge zero, a2, 4 -# CHECK-S-OBJ: blez a2, 4 +# CHECK-S-NOALIAS: bge zero, a2, 4 +# CHECK-S: blez a2, 4 +# CHECK-OBJ-NOALIAS: bge zero, a2, 0x38 +# CHECK-OBJ: blez a2, 0x38 blez x12, 4 -# CHECK-S-OBJ-NOALIAS: bge a3, zero, 8 -# CHECK-S-OBJ: bgez a3, 8 +# CHECK-S-NOALIAS: bge a3, zero, 8 +# CHECK-S: bgez a3, 8 +# CHECK-OBJ-NOALIAS: bge a3, zero, 0x40 +# CHECK-OBJ: bgez a3, 0x40 bgez x13, 8 -# CHECK-S-OBJ-NOALIAS: blt a4, zero, 12 -# CHECK-S-OBJ: bltz a4, 12 +# CHECK-S-NOALIAS: blt a4, zero, 12 +# CHECK-S: bltz a4, 12 +# CHECK-OBJ-NOALIAS: blt a4, zero, 0x48 +# CHECK-OBJ: bltz a4, 0x48 bltz x14, 12 -# CHECK-S-OBJ-NOALIAS: blt zero, a5, 16 -# CHECK-S-OBJ: bgtz a5, 16 +# CHECK-S-NOALIAS: blt zero, a5, 16 +# CHECK-S: bgtz a5, 16 +# CHECK-OBJ-NOALIAS: blt zero, a5, 0x50 +# CHECK-OBJ: bgtz a5, 0x50 bgtz x15, 16 # Always output the canonical mnemonic for the pseudo branch instructions. -# CHECK-S-OBJ-NOALIAS: blt a6, a5, 20 -# CHECK-S-OBJ: blt a6, a5, 20 +# CHECK-S-NOALIAS: blt a6, a5, 20 +# CHECK-S: blt a6, a5, 20 +# CHECK-OBJ-NOALIAS: blt a6, a5, 0x58 +# CHECK-OBJ: blt a6, a5, 0x58 bgt x15, x16, 20 -# CHECK-S-OBJ-NOALIAS: bge a7, a6, 24 -# CHECK-S-OBJ: bge a7, a6, 24 +# CHECK-S-NOALIAS: bge a7, a6, 24 +# CHECK-S: bge a7, a6, 24 +# CHECK-OBJ-NOALIAS: bge a7, a6, 0x60 +# CHECK-OBJ: bge a7, a6, 0x60 ble x16, x17, 24 -# CHECK-S-OBJ-NOALIAS: bltu s2, a7, 28 -# CHECK-S-OBJ: bltu s2, a7, 28 +# CHECK-S-NOALIAS: bltu s2, a7, 28 +# CHECK-S: bltu s2, a7, 28 +# CHECK-OBJ-NOALIAS: bltu s2, a7, 0x68 +# CHECK-OBJ: bltu s2, a7, 0x68 bgtu x17, x18, 28 -# CHECK-S-OBJ-NOALIAS: bgeu s3, s2, 32 -# CHECK-S-OBJ: bgeu s3, s2, 32 +# CHECK-S-NOALIAS: bgeu s3, s2, 32 +# CHECK-S: bgeu s3, s2, 32 +# CHECK-OBJ-NOALIAS: bgeu s3, s2, 0x70 +# CHECK-OBJ: bgeu s3, s2, 0x70 bleu x18, x19, 32 -# CHECK-S-OBJ-NOALIAS: jal zero, 2044 -# CHECK-S-OBJ: j 2044 +# CHECK-S-NOALIAS: jal zero, 2044 +# CHECK-S: j 2044 +# CHECK-OBJ-NOALIAS: jal zero, 0x850 +# CHECK-OBJ: j 0x850 j 2044 # CHECK-S-NOALIAS: jal zero, foo # CHECK-S: j foo @@ -124,8 +146,10 @@ j a0 # CHECK-OBJ-NOALIAS: jal zero, 0 # CHECK-OBJ: j 0 j . -# CHECK-S-OBJ-NOALIAS: jal ra, 2040 -# CHECK-S-OBJ: jal 2040 +# CHECK-S-NOALIAS: jal ra, 2040 +# CHECK-S: jal 2040 +# CHECK-OBJ-NOALIAS: jal ra, 0x85c +# CHECK-OBJ: jal 0x85c jal 2040 # CHECK-S-NOALIAS: jal ra, foo # CHECK-S: jal foo diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s index 94f6556ea10c..94e9b5fe9da5 100644 --- a/llvm/test/MC/RISCV/rvv/snippet.s +++ b/llvm/test/MC/RISCV/rvv/snippet.s @@ -29,4 +29,4 @@ loop: sub a0, a0, a3 # Decrement count # CHECK-INST: 33 05 d5 40 sub a0, a0, a3 bnez a0, loop # Any more? -# CHECK-INST: e3 1a 05 fc bnez a0, -44 +# CHECK-INST: e3 1a 05 fc bnez a0, 0x0 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
