Author: Jessica Paquette Date: 2020-12-01T16:45:37-08:00 New Revision: c82f002cea304be505f14af70dce25ad149ba29f
URL: https://github.com/llvm/llvm-project/commit/c82f002cea304be505f14af70dce25ad149ba29f DIFF: https://github.com/llvm/llvm-project/commit/c82f002cea304be505f14af70dce25ad149ba29f.diff LOG: [AArch64][GlobalISel] Don't write to WZR in non-flag-setting G_BRCOND case We are avoiding writing to WZR just about everywhere else. Also update the code to use MachineIRBuilder for the sake of consistency. We also didn't have a GlobalISel testcase for this path, so add a simple one now. Differential Revision: https://reviews.llvm.org/D90626 Added: llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir Modified: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index 3dba92eea3d3..610bf3af8793 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -2123,16 +2123,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { I.eraseFromParent(); return constrainSelectedInstRegOperands(*TestBit, TII, TRI, RBI); } else { - auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri)) - .addDef(AArch64::WZR) - .addUse(CondReg) + auto CMP = MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}) .addImm(1); - constrainSelectedInstRegOperands(*CMP.getInstr(), TII, TRI, RBI); + constrainSelectedInstRegOperands(*CMP, TII, TRI, RBI); auto Bcc = - BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc)) - .addImm(AArch64CC::EQ) - .addMBB(DestMBB); - + MIB.buildInstr(AArch64::Bcc).addImm(AArch64CC::EQ).addMBB(DestMBB); I.eraseFromParent(); return constrainSelectedInstRegOperands(*Bcc.getInstr(), TII, TRI, RBI); } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir b/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir new file mode 100644 index 000000000000..23bc998003c0 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s\ +# +# Verify that when a function has the speculative_load_hardening attribute we +# never produce a CB(N)Z or TB(N)Z. +# + +--- | + define void @no_tbnz() speculative_load_hardening { ret void } + define void @no_cbz() speculative_load_hardening { ret void } +... + +--- +name: no_tbnz +legalized: true +regBankSelected: true +body: | + ; CHECK-LABEL: name: no_tbnz + ; CHECK: bb.0: + ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) + ; CHECK: %reg:gpr32 = COPY $w0 + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg, 1, implicit-def $nzcv + ; CHECK: Bcc 0, %bb.1, implicit $nzcv + ; CHECK: B %bb.0 + ; CHECK: bb.1: + ; CHECK: RET_ReallyLR + bb.0: + liveins: $w0 + successors: %bb.0, %bb.1 + %reg:gpr(s32) = COPY $w0 + %cond:gpr(s1) = G_TRUNC %reg + G_BRCOND %cond(s1), %bb.1 + G_BR %bb.0 + bb.1: + RET_ReallyLR +... +--- +name: no_cbz +legalized: true +regBankSelected: true +body: | + ; CHECK-LABEL: name: no_cbz + ; CHECK: bb.0: + ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) + ; CHECK: %reg:gpr32sp = COPY $w0 + ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 0, 0, implicit-def $nzcv + ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv + ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cmp, 1, implicit-def $nzcv + ; CHECK: Bcc 0, %bb.1, implicit $nzcv + ; CHECK: B %bb.0 + ; CHECK: bb.1: + ; CHECK: RET_ReallyLR + bb.0: + liveins: $w0 + successors: %bb.0, %bb.1 + %reg:gpr(s32) = COPY $w0 + %zero:gpr(s32) = G_CONSTANT i32 0 + %cmp:gpr(s32) = G_ICMP intpred(eq), %reg, %zero + %cond:gpr(s1) = G_TRUNC %cmp(s32) + G_BRCOND %cond(s1), %bb.1 + G_BR %bb.0 + bb.1: + RET_ReallyLR +... _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
