Author: Francesco Petrogalli Date: 2020-11-30T17:38:51Z New Revision: f6150aa41a48ac8b5372fe4d6ccdfff96e432431
URL: https://github.com/llvm/llvm-project/commit/f6150aa41a48ac8b5372fe4d6ccdfff96e432431 DIFF: https://github.com/llvm/llvm-project/commit/f6150aa41a48ac8b5372fe4d6ccdfff96e432431.diff LOG: [SelectionDAGBuilder] Update signature of `getRegsAndSizes()`. The mapping between registers and relative size has been updated to use TypeSize to account for the size of scalable EVTs. The patch is a NFCI, if not for the fact that with this change the function `getUnderlyingArgRegs` does not raise a warning for implicit conversion of `TypeSize` to `unsigned` when generating machine code from the test added to the patch. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D92096 Added: llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll Modified: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index dd5beb33ecce..9d2174f4b85a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -980,14 +980,14 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, } } -SmallVector<std::pair<unsigned, unsigned>, 4> +SmallVector<std::pair<unsigned, TypeSize>, 4> RegsForValue::getRegsAndSizes() const { - SmallVector<std::pair<unsigned, unsigned>, 4> OutVec; + SmallVector<std::pair<unsigned, TypeSize>, 4> OutVec; unsigned I = 0; for (auto CountAndVT : zip_first(RegCount, RegVTs)) { unsigned RegCount = std::get<0>(CountAndVT); MVT RegisterVT = std::get<1>(CountAndVT); - unsigned RegisterSize = RegisterVT.getSizeInBits(); + TypeSize RegisterSize = RegisterVT.getSizeInBits(); for (unsigned E = I + RegCount; I != E; ++I) OutVec.push_back(std::make_pair(Regs[I], RegisterSize)); } @@ -5317,7 +5317,7 @@ static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, // getUnderlyingArgRegs - Find underlying registers used for a truncated, // bitcasted, or split argument. Returns a list of <Register, size in bits> static void -getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, +getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, TypeSize>> &Regs, const SDValue &N) { switch (N.getOpcode()) { case ISD::CopyFromReg: { @@ -5428,7 +5428,7 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( if (FI != std::numeric_limits<int>::max()) Op = MachineOperand::CreateFI(FI); - SmallVector<std::pair<unsigned, unsigned>, 8> ArgRegsAndSizes; + SmallVector<std::pair<unsigned, TypeSize>, 8> ArgRegsAndSizes; if (!Op && N.getNode()) { getUnderlyingArgRegs(ArgRegsAndSizes, N); Register Reg; @@ -5458,8 +5458,8 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue( if (!Op) { // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg - auto splitMultiRegDbgValue - = [&](ArrayRef<std::pair<unsigned, unsigned>> SplitRegs) { + auto splitMultiRegDbgValue = [&](ArrayRef<std::pair<unsigned, TypeSize>> + SplitRegs) { unsigned Offset = 0; for (auto RegAndSize : SplitRegs) { // If the expression is already a fragment, the current register diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index 89b5de0a9f21..bf2023674342 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -895,7 +895,7 @@ struct RegsForValue { } /// Return a list of registers and their sizes. - SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const; + SmallVector<std::pair<unsigned, TypeSize>, 4> getRegsAndSizes() const; }; } // end namespace llvm diff --git a/llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll b/llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll new file mode 100644 index 000000000000..5a519bea2a70 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll @@ -0,0 +1,30 @@ +; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s +; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t + +; If this check fails please read +; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on +; how to resolve it. + +; WARN-NOT: warning + +; CHECK-LABEL: do_something: +define <vscale x 2 x double> @do_something(<vscale x 2 x double> %vx) { +entry: + call void @llvm.dbg.value(metadata <vscale x 2 x double> %vx, metadata !3, metadata !DIExpression()), !dbg !5 + %0 = tail call <vscale x 2 x double> @f(<vscale x 2 x double> %vx) + ret <vscale x 2 x double> %0 +} + +declare <vscale x 2 x double> @f(<vscale x 2 x double>) + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1) +!1 = !DIFile(filename: "file.c", directory: "/") +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = !DILocalVariable(scope: !4) +!4 = distinct !DISubprogram(unit: !0) +!5 = !DILocation(scope: !4) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
