Author: Raul Tambre Date: 2020-11-25T19:18:04-05:00 New Revision: e4500bab8b29bdea2f4c51e8a143b8122491e6f5
URL: https://github.com/llvm/llvm-project/commit/e4500bab8b29bdea2f4c51e8a143b8122491e6f5 DIFF: https://github.com/llvm/llvm-project/commit/e4500bab8b29bdea2f4c51e8a143b8122491e6f5.diff LOG: [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass() TargetRegisterInfo::getMinimalPhysRegClass() returns rtcGPR64RegClassID for X16 and X17, as it's the last matching class. This in turn gets passed to AArch64RegisterBankInfo::getRegBankFromRegClass(), which hits an unreachable. It seems sensible to handle this case, so copies from X16 and X17 work. Copying from X17 is used in inline assembly in libunwind for pointer authentication. Differential Revision: https://reviews.llvm.org/D85720 (cherry picked from commit e887d0e89b837be37b4279735a9c1ac57e90c995) Added: Modified: llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp index 7e3ff1948dad..93213f5977e5 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp @@ -261,6 +261,7 @@ AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, case AArch64::GPR64common_and_GPR64noipRegClassID: case AArch64::GPR64noip_and_tcGPR64RegClassID: case AArch64::tcGPR64RegClassID: + case AArch64::rtcGPR64RegClassID: case AArch64::WSeqPairsClassRegClassID: case AArch64::XSeqPairsClassRegClassID: return getRegBank(AArch64::GPRRegBankID); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir index e226c0fbae7d..09884c75409e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir @@ -75,6 +75,8 @@ define void @test_gphi_ptr() { ret void } + define void @test_restricted_tail_call() { ret void } + ... --- @@ -888,3 +890,20 @@ body: | RET_ReallyLR implicit $x0 ... + +--- +name: test_restricted_tail_call +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x16, $x17 + ; CHECK-LABEL: name: test_restricted_tail_call + ; CHECK: liveins: $x16, $x17 + ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x16 + ; CHECK: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x17 + ; CHECK: RET_ReallyLR + %0:_(s64) = COPY $x16 + %1:_(s64) = COPY $x17 + RET_ReallyLR +... _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
