Author: hans
Date: Tue Feb 12 02:45:41 2019
New Revision: 353822
URL: http://llvm.org/viewvc/llvm-project?rev=353822&view=rev
Log:
Merging r353308 and r353383:
------------------------------------------------------------------------
r353308 | tnorthover | 2019-02-06 16:26:35 +0100 (Wed, 06 Feb 2019) | 5 lines
AArch64: enforce even/odd register pairs for CASP instructions.
ARMv8.1a CASP instructions need the first of the pair to be an even register
(otherwise the encoding is unallocated). We enforced this during assembly, but
not CodeGen before.
------------------------------------------------------------------------
------------------------------------------------------------------------
r353383 | tnorthover | 2019-02-07 11:35:34 +0100 (Thu, 07 Feb 2019) | 4 lines
AArch64: implement copy for paired GPR registers.
When doing 128-bit atomics using CASP we might need to copy a GPRPair to a
different register, but that was unimplemented up to now.
------------------------------------------------------------------------
Added:
llvm/branches/release_80/test/CodeGen/AArch64/cmpxchg-lse-even-regs.ll
- copied unchanged from r353308,
llvm/trunk/test/CodeGen/AArch64/cmpxchg-lse-even-regs.ll
llvm/branches/release_80/test/CodeGen/AArch64/seqpaircopy.mir
- copied unchanged from r353383,
llvm/trunk/test/CodeGen/AArch64/seqpaircopy.mir
Modified:
llvm/branches/release_80/ (props changed)
llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.h
llvm/branches/release_80/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/branches/release_80/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Propchange: llvm/branches/release_80/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 12 02:45:41 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,351325,351344-351345,351349,351351,351370,351381,351387,351421,351426,351436,351475,351485,351753-351754,351765,351910,351930,351932,352034,352204,352246,352374,352555,352607-352608,352770,352889,352945,353015,353061,353082,353138,353141,353155,353218,353304,353334,353367,353374,353463,353489,353551,353809
+/llvm/trunk:155241,351325,351344-351345,351349,351351,351370,351381,351387,351421,351426,351436,351475,351485,351753-351754,351765,351910,351930,351932,352034,352204,352246,352374,352555,352607-352608,352770,352889,352945,353015,353061,353082,353138,353141,353155,353218,353304,353308,353334,353367,353374,353383,353463,353489,353551,353809
Modified: llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=353822&r1=353821&r2=353822&view=diff
==============================================================================
--- llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Feb 12
02:45:41 2019
@@ -2292,6 +2292,31 @@ void AArch64InstrInfo::copyPhysRegTuple(
}
}
+void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ DebugLoc DL, unsigned DestReg,
+ unsigned SrcReg, bool KillSrc,
+ unsigned Opcode, unsigned ZeroReg,
+ llvm::ArrayRef<unsigned> Indices) const
{
+ const TargetRegisterInfo *TRI = &getRegisterInfo();
+ unsigned NumRegs = Indices.size();
+
+#ifndef NDEBUG
+ uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
+ uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
+ assert(DestEncoding % NumRegs == 0 && SrcEncoding % NumRegs == 0 &&
+ "GPR reg sequences should not be able to overlap");
+#endif
+
+ for (unsigned SubReg = 0; SubReg != NumRegs; ++SubReg) {
+ const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
+ AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
+ MIB.addReg(ZeroReg);
+ AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
+ MIB.addImm(0);
+ }
+}
+
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, unsigned DestReg,
@@ -2431,6 +2456,22 @@ void AArch64InstrInfo::copyPhysReg(Machi
return;
}
+ if (AArch64::XSeqPairsClassRegClass.contains(DestReg) &&
+ AArch64::XSeqPairsClassRegClass.contains(SrcReg)) {
+ static const unsigned Indices[] = {AArch64::sube64, AArch64::subo64};
+ copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRXrs,
+ AArch64::XZR, Indices);
+ return;
+ }
+
+ if (AArch64::WSeqPairsClassRegClass.contains(DestReg) &&
+ AArch64::WSeqPairsClassRegClass.contains(SrcReg)) {
+ static const unsigned Indices[] = {AArch64::sube32, AArch64::subo32};
+ copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs,
+ AArch64::WZR, Indices);
+ return;
+ }
+
if (AArch64::FPR128RegClass.contains(DestReg) &&
AArch64::FPR128RegClass.contains(SrcReg)) {
if (Subtarget.hasNEON()) {
Modified: llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.h?rev=353822&r1=353821&r2=353822&view=diff
==============================================================================
--- llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/branches/release_80/lib/Target/AArch64/AArch64InstrInfo.h Tue Feb 12
02:45:41 2019
@@ -122,6 +122,10 @@ public:
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc, unsigned Opcode,
llvm::ArrayRef<unsigned> Indices) const;
+ void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ DebugLoc DL, unsigned DestReg, unsigned SrcReg,
+ bool KillSrc, unsigned Opcode, unsigned ZeroReg,
+ llvm::ArrayRef<unsigned> Indices) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
Modified: llvm/branches/release_80/lib/Target/AArch64/AArch64RegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/lib/Target/AArch64/AArch64RegisterInfo.td?rev=353822&r1=353821&r2=353822&view=diff
==============================================================================
--- llvm/branches/release_80/lib/Target/AArch64/AArch64RegisterInfo.td
(original)
+++ llvm/branches/release_80/lib/Target/AArch64/AArch64RegisterInfo.td Tue Feb
12 02:45:41 2019
@@ -649,10 +649,12 @@ def FPR128Op : RegisterOperand<FPR128, "
// ARMv8.1a atomic CASP register operands
-def WSeqPairs : RegisterTuples<[sube32, subo32],
- [(rotl GPR32, 0), (rotl GPR32, 1)]>;
-def XSeqPairs : RegisterTuples<[sube64, subo64],
- [(rotl GPR64, 0), (rotl GPR64, 1)]>;
+def WSeqPairs : RegisterTuples<[sube32, subo32],
+ [(decimate (rotl GPR32, 0), 2),
+ (decimate (rotl GPR32, 1), 2)]>;
+def XSeqPairs : RegisterTuples<[sube64, subo64],
+ [(decimate (rotl GPR64, 0), 2),
+ (decimate (rotl GPR64, 1), 2)]>;
def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
(add WSeqPairs)>{
Modified:
llvm/branches/release_80/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=353822&r1=353821&r2=353822&view=diff
==============================================================================
---
llvm/branches/release_80/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
(original)
+++
llvm/branches/release_80/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Tue Feb 12 02:45:41 2019
@@ -1779,8 +1779,8 @@ static DecodeStatus DecodeGPRSeqPairsCla
if (RegNo & 0x1)
return Fail;
- unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
- Inst.addOperand(MCOperand::createReg(Register));
+ unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
+ Inst.addOperand(MCOperand::createReg(Reg));
return Success;
}
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