Author: hans Date: Tue Aug 21 15:49:06 2018 New Revision: 340355 URL: http://llvm.org/viewvc/llvm-project?rev=340355&view=rev Log: Merging r340158: ------------------------------------------------------------------------ r340158 | s.desmalen | 2018-08-20 11:16:59 +0200 (Mon, 20 Aug 2018) | 16 lines
[AArch64][SVE] Asm: Add SVE System registers This patch adds system registers for controlling aspects of SVE: - ZCR_EL1 (r/w) visible at EL1 and EL0. - ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0. - ZCR_EL3 (r/w) visible at all exception levels. and a system register identifying SVE: - ID_AA64ZFR0_EL1 (r) SVE Feature identifier. Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D50885 ------------------------------------------------------------------------ Added: llvm/branches/release_70/test/MC/AArch64/SVE/system-regs-diagnostics.s - copied unchanged from r340158, llvm/trunk/test/MC/AArch64/SVE/system-regs-diagnostics.s llvm/branches/release_70/test/MC/AArch64/SVE/system-regs.s - copied unchanged from r340158, llvm/trunk/test/MC/AArch64/SVE/system-regs.s Modified: llvm/branches/release_70/ (props changed) llvm/branches/release_70/lib/Target/AArch64/AArch64SystemOperands.td Propchange: llvm/branches/release_70/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Tue Aug 21 15:49:06 2018 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339769,339822,339883,339895-339896,339945 +/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339769,339822,339883,339895-339896,339945,340158 Modified: llvm/branches/release_70/lib/Target/AArch64/AArch64SystemOperands.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/AArch64/AArch64SystemOperands.td?rev=340355&r1=340354&r2=340355&view=diff ============================================================================== --- llvm/branches/release_70/lib/Target/AArch64/AArch64SystemOperands.td (original) +++ llvm/branches/release_70/lib/Target/AArch64/AArch64SystemOperands.td Tue Aug 21 15:49:06 2018 @@ -576,6 +576,12 @@ def : ROSysReg<"ICH_VTR_EL2", 0b1 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; +// SVE control registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureSVE} }] in { +def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; +} + // v8.1a "Limited Ordering Regions" extension-specific system register // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_1aOps} }] in @@ -1311,6 +1317,15 @@ def : RWSysReg<"VNCR_EL2", 0b11, } // HasV8_4aOps +// SVE control registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureSVE} }] in { +def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; +} + // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcCyclone} }] in _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
