Author: David Spickett Date: 2024-08-12T11:03:06Z New Revision: afe019ca93a72a5969d82cfff5018f3dd79dc75a
URL: https://github.com/llvm/llvm-project/commit/afe019ca93a72a5969d82cfff5018f3dd79dc75a DIFF: https://github.com/llvm/llvm-project/commit/afe019ca93a72a5969d82cfff5018f3dd79dc75a.diff LOG: [lldb][test][AArch64] Regex match field values in register test As these are flags they can be set or not depending on what the system libraries did prior to loading the program. Added: Modified: lldb/test/API/commands/register/register/register_command/TestRegisters.py Removed: ################################################################################ diff --git a/lldb/test/API/commands/register/register/register_command/TestRegisters.py b/lldb/test/API/commands/register/register/register_command/TestRegisters.py index d1fc3e100af332..bfd7a382064e9d 100644 --- a/lldb/test/API/commands/register/register/register_command/TestRegisters.py +++ b/lldb/test/API/commands/register/register/register_command/TestRegisters.py @@ -628,11 +628,16 @@ def test_register_read_fields(self): self.common_setup() # N/Z/C/V bits will always be present, so check only for those. - self.expect("register read cpsr", substrs=["= (N = 0, Z = 1, C = 1, V = 0"]) - self.expect("register read fpsr", substrs=["= (QC = 0, IDC = 0, IXC = 0"]) - # AHP/DN/FZ/RMode always present, others may vary. self.expect( - "register read fpcr", substrs=["= (AHP = 0, DN = 0, FZ = 0, RMode = RN"] + "register read cpsr", + patterns=["= \(N = [0|1], Z = [0|1], C = [0|1], V = [0|1]"], + ) + self.expect( + "register read fpsr", patterns=["= \(QC = [0|1], IDC = [0|1], IXC = [0|1]"] + ) + # AHP/DN/FZ always present, others may vary. + self.expect( + "register read fpcr", patterns=["= \(AHP = [0|1], DN = [0|1], FZ = [0|1]"] ) # Should get enumerator descriptions for RMode. _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
