https://github.com/jimingham created
https://github.com/llvm/llvm-project/pull/88535
The only change is a fix for the "register" iterator test to not rely on
particular register names.
I mistook where the artificial "pc" register is generated. It isn't added to
the register list or the register sets (except on arm where that's the name of
the actual register), so I can't use it in this test. I instead just assert
that the "register" generator produces the same list as flattening the register
sets from "registers".
This reverts commit 9f14914753599f3879e4c273191959e2f1b3632c.
>From 4a335c835239edc1989a1ddd7875a6e6edd2d143 Mon Sep 17 00:00:00 2001
From: Jim Ingham <jing...@apple.com>
Date: Fri, 12 Apr 2024 08:52:43 -0700
Subject: [PATCH] Reapply "Fix error in unrecognized register name handling for
"SBFrame.register"" (#88468)" with a fix for the "register" iterator test to
not rely on particular register names.
I mistook where the artificial "pc" register is generated. It isn't added to
the register
list or the register sets (except on arm where that's the name of the actual
register), so
I can't use it in this test. I instead just assert that the "register"
generator produces
the same list as flattening the register sets from "registers".
This reverts commit 9f14914753599f3879e4c273191959e2f1b3632c.
---
lldb/bindings/interface/SBFrameExtensions.i | 12 +++++++++++-
lldb/test/API/python_api/frame/TestFrames.py | 16 ++++++++++++++--
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/lldb/bindings/interface/SBFrameExtensions.i
b/lldb/bindings/interface/SBFrameExtensions.i
index 43b22ed7a6b325..e0472280666ab9 100644
--- a/lldb/bindings/interface/SBFrameExtensions.i
+++ b/lldb/bindings/interface/SBFrameExtensions.i
@@ -44,6 +44,16 @@ STRING_EXTENSION_OUTSIDE(SBFrame)
def __init__(self, regs):
self.regs = regs
+ def __iter__(self):
+ return self.get_registers()
+
+ def get_registers(self):
+ for i in range(0,len(self.regs)):
+ rs = self.regs[i]
+ for j in range (0,rs.num_children):
+ reg = rs.GetChildAtIndex(j)
+ yield reg
+
def __getitem__(self, key):
if type(key) is str:
for i in range(0,len(self.regs)):
@@ -52,7 +62,7 @@ STRING_EXTENSION_OUTSIDE(SBFrame)
reg = rs.GetChildAtIndex(j)
if reg.name == key: return reg
else:
- return lldb.SBValue()
+ return SBValue()
return registers_access(self.registers)
diff --git a/lldb/test/API/python_api/frame/TestFrames.py
b/lldb/test/API/python_api/frame/TestFrames.py
index a82b129bc8099d..0ec12206024ab7 100644
--- a/lldb/test/API/python_api/frame/TestFrames.py
+++ b/lldb/test/API/python_api/frame/TestFrames.py
@@ -73,10 +73,12 @@ def test_get_arg_vals_for_call_stack(self):
gpr_reg_set = lldbutil.get_GPRs(frame)
pc_value = gpr_reg_set.GetChildMemberWithName("pc")
self.assertTrue(pc_value, "We should have a valid PC.")
- pc_value_int = int(pc_value.GetValue(), 0)
+
+
# Make sure on arm targets we dont mismatch PC value on the
basis of thumb bit.
# Frame PC will not have thumb bit set in case of a thumb
# instruction as PC.
+ pc_value_int = int(pc_value.GetValue(), 0)
if self.getArchitecture() in ["arm", "armv7", "armv7k"]:
pc_value_int &= ~1
self.assertEqual(
@@ -91,7 +93,17 @@ def test_get_arg_vals_for_call_stack(self):
frame.GetSP(),
"SP gotten as a value should equal frame's GetSP",
)
-
+ # Test that the "register" property's flat list matches the
list from
+ # the "registers" property that returns register sets:
+ register_regs = set()
+ flattened_regs = set()
+ for reg_set in frame.registers:
+ for reg in reg_set:
+ flattened_regs.add(reg.name)
+ for reg in frame.register:
+ register_regs.add(reg.name)
+ self.assertEqual(register_regs, flattened_regs, "register
matches registers")
+
print("---", file=session)
process.Continue()
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