================
@@ -8310,6 +8310,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+ SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ unsigned Opc = N->getOpcode();
+ EVT VT = N->getValueType(0);
+ EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ bool IsMax = Opc == ISD::FMAXIMUM;
+
+ if (VT.isVector() &&
+ isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType()))
+ return SDValue();
+
+ // First, implement comparison not propagating NaN. If no native fmin or fmax
+ // available, use plain select with setcc instead.
+ SDValue MinMax;
+ unsigned CompOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
+ unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM;
+ if (isOperationLegalOrCustom(CompOpcIeee, VT)) {
+ MinMax = DAG.getNode(CompOpcIeee, DL, VT, LHS, RHS);
+ } else if (isOperationLegalOrCustom(CompOpc, VT)) {
+ MinMax = DAG.getNode(CompOpc, DL, VT, LHS, RHS);
+ } else {
+ // NaN (if exists) will be propagated later, so orderness doesn't matter.
+ SDValue Compare =
+ DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);
+ MinMax = DAG.getSelect(DL, VT, Compare, LHS, RHS);
+ }
+
+ // Propagate any NaN of both operands
+ if (!N->getFlags().hasNoNaNs() &&
+ (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
----------------
arsenm wrote:
Should invert the order of these checks. RHS is canonically simpler / cheaper
to inspect
https://github.com/llvm/llvm-project/pull/67301
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