DianQK wrote: > I don't believe the undef is the issue - I think the issue is that > AArch64InstrInfo::isCopyInstrImpl is saying that a W-reg orr is a copy, even > if it is really a zextend because the entire X output register is depended > upon.
Thanks for the explanation. > Can you try and add something to isCopyInstrImpl instead, that says: If the > register is virtual then it should not be a subreg, and if the register is > physical then there should not be an implicit def of the X reg. Would that > solve your issue, and would it cause other problems in AArch64 codegen? Thanks I'm not sure if I'm misunderstanding anything. But I tried to file the #75184 PR. It breaks the original commit https://github.com/llvm/llvm-project/commit/53726588f672a915c6f907569356091552500f23. It looks like it's because we're generating the mov instruction for the ORRWsr. (At this point this is a copy instruction?) I'm not sure exactly what is going wrong. Maybe we need to add a new method to TargetRegisterInfo? Or are you going to fix this issue? I'm not familiar with MIR. Alternatively, we can add implicit-def to MachineCopyPropagation? But that doesn't seem right either. https://github.com/llvm/llvm-project/pull/74682 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
