Author: David Spickett Date: 2023-09-13T10:07:36+01:00 New Revision: 11de4c724c8e875f75c2d1c733c38051bc818601
URL: https://github.com/llvm/llvm-project/commit/11de4c724c8e875f75c2d1c733c38051bc818601 DIFF: https://github.com/llvm/llvm-project/commit/11de4c724c8e875f75c2d1c733c38051bc818601.diff LOG: [lldb][AArch64] Add tests for SME's SVE register state to TestArm64DynamicRegsets SME reuses SVE's register state but adds new modes to it. Therefore we can't check all those in the same test as the existing SVE checks. SME's ZA, SVG and SVCR register checks will be added to this test in later patches. Prior to this we didn't have any testing of writing streaming mode SVE registers from lldb, only writing SVE registers in normal (non-streaming) SVE mode. Reviewed By: omjavaid Differential Revision: https://reviews.llvm.org/D157846 Added: Modified: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c Removed: ################################################################################ diff --git a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py index 1decdd43969ef2a..e91eeba2a601ebc 100644 --- a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py +++ b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py @@ -120,3 +120,37 @@ def test_aarch64_dynamic_regset_config(self): ) self.expect("register read data_mask", substrs=["data_mask = 0x"]) self.expect("register read code_mask", substrs=["code_mask = 0x"]) + + @no_debug_info_test + @skipIf(archs=no_match(["aarch64"])) + @skipIf(oslist=no_match(["linux"])) + def test_aarch64_dynamic_regset_config_sme(self): + """Test AArch64 Dynamic Register sets configuration, but only SME + registers.""" + if not self.isAArch64SME(): + self.skipTest("SME must be present.") + + self.build() + self.line = line_number("main.c", "// Set a break point here.") + + exe = self.getBuildArtifact("a.out") + self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET) + + lldbutil.run_break_set_by_file_and_line( + self, "main.c", self.line, num_expected_locations=1 + ) + self.runCmd("settings set target.run-args sme") + self.runCmd("run", RUN_SUCCEEDED) + + self.expect( + "thread backtrace", + STOPPED_DUE_TO_BREAKPOINT, + substrs=["stop reason = breakpoint 1."], + ) + + register_sets = self.thread().GetSelectedFrame().GetRegisters() + + ssve_registers = register_sets.GetFirstValueByName( + "Scalable Vector Extension Registers") + self.assertTrue(ssve_registers.IsValid()) + self.sve_regs_read_dynamic(ssve_registers) diff --git a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c index 6ed25c4eb6a098f..b8db8852b8ed51a 100644 --- a/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c +++ b/lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c @@ -1,5 +1,9 @@ #include <sys/auxv.h> +#ifndef HWCAP2_SME +#define HWCAP2_SME (1 << 23) +#endif + void set_sve_registers() { // AArch64 SVE extension ISA adds a new set of vector and predicate registers: // 32 Z registers, 16 P registers, and 1 FFR register. @@ -64,8 +68,14 @@ void set_sve_registers() { asm volatile("cpy z31.b, p15/z, #32\n\t"); } -int main() { - if (getauxval(AT_HWCAP) & HWCAP_SVE) // check if SVE is present +int main(int argc, char *argv[]) { + if (argc > 1) { + // Enable streaming mode SVE and the ZA array storage. + asm volatile("msr s0_3_c4_c7_3, xzr" /*smstart*/); + } + + // If we have SVE or SME, set the SVE registers. + if ((getauxval(AT_HWCAP) & HWCAP_SVE) || (getauxval(AT_HWCAP2) & HWCAP2_SME)) set_sve_registers(); return 0; // Set a break point here. _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
