Author: Teizhu Yang Date: 2022-11-10T13:49:11+08:00 New Revision: 97842fcba9e3a3fa4db52a47215641f9141fea63
URL: https://github.com/llvm/llvm-project/commit/97842fcba9e3a3fa4db52a47215641f9141fea63 DIFF: https://github.com/llvm/llvm-project/commit/97842fcba9e3a3fa4db52a47215641f9141fea63.diff LOG: [LLDB] Add LoongArch software breakpoint trap opcode Use `break 0x5` for LoongArch software breakpoint traps. The magic number 0x5 means `BRK_SSTEPBP` as defined in the kernel header `asm/break.h` on LoongArch. Reviewed By: SixWeining, xen0n Differential Revision: https://reviews.llvm.org/D137519 Added: Modified: lldb/source/Host/common/NativeProcessProtocol.cpp lldb/source/Target/Platform.cpp Removed: ################################################################################ diff --git a/lldb/source/Host/common/NativeProcessProtocol.cpp b/lldb/source/Host/common/NativeProcessProtocol.cpp index cdb59842e658b..21f382da2f229 100644 --- a/lldb/source/Host/common/NativeProcessProtocol.cpp +++ b/lldb/source/Host/common/NativeProcessProtocol.cpp @@ -507,6 +507,8 @@ NativeProcessProtocol::GetSoftwareBreakpointTrapOpcode(size_t size_hint) { static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak + static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a, + 0x00}; // break 0x5 switch (GetArchitecture().GetMachine()) { case llvm::Triple::aarch64: @@ -541,6 +543,10 @@ NativeProcessProtocol::GetSoftwareBreakpointTrapOpcode(size_t size_hint) { : llvm::makeArrayRef(g_riscv_opcode); } + case llvm::Triple::loongarch32: + case llvm::Triple::loongarch64: + return llvm::makeArrayRef(g_loongarch_opcode); + default: return llvm::createStringError(llvm::inconvertibleErrorCode(), "CPU type not supported!"); @@ -567,6 +573,8 @@ size_t NativeProcessProtocol::GetSoftwareBreakpointPCOffset() { case llvm::Triple::ppc64le: case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::loongarch32: + case llvm::Triple::loongarch64: // On these architectures the PC doesn't get updated for breakpoint hits. return 0; diff --git a/lldb/source/Target/Platform.cpp b/lldb/source/Target/Platform.cpp index 306ee99be5952..7bb2b1ccf7cbb 100644 --- a/lldb/source/Target/Platform.cpp +++ b/lldb/source/Target/Platform.cpp @@ -1939,6 +1939,14 @@ size_t Platform::GetSoftwareBreakpointTrapOpcode(Target &target, } } break; + case llvm::Triple::loongarch32: + case llvm::Triple::loongarch64: { + static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a, + 0x00}; // break 0x5 + trap_opcode = g_loongarch_opcode; + trap_opcode_size = sizeof(g_loongarch_opcode); + } break; + default: return 0; } _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
