Emmmer added a comment. In D130342#3711534 <https://reviews.llvm.org/D130342#3711534>, @tzb99 wrote:
> In D130342#3710299 <https://reviews.llvm.org/D130342#3710299>, @Emmmer wrote: > >> In D130342#3710122 <https://reviews.llvm.org/D130342#3710122>, @tzb99 wrote: >> >>> In D130342#3709772 <https://reviews.llvm.org/D130342#3709772>, @Emmmer >>> wrote: >>> >>>> What is implemented: >>>> >>>> - Use the same register layout as Linux kernel and mock read/write for >>>> `x0` register (the always zero register). >>>> - Take RISC-V `ebreak` instruction as breakpoint trap code, so our >>>> breakpoint works as expected now. >>>> - Refactor some duplicate code. >>>> >>>> Further work: >>>> >>>> - RISC-V does not support hardware single stepping yet. A software >>>> implementation may come in future PR. >>>> - Add support for RVC extension (the trap code, etc.). >>> >>> Thank you so much for the contribution! I have few more questions. What is >>> your qemu spec? Is it operated in the user mode or the system mode? In >>> addition, did your cross compilation build using in-tree build or build >>> lldb separately? >> >> I'm using qemu-system 7.0.0 and in-tree cross build. > > I am sorry to bother you again, is the dwarf header file changed since the > last diff? I noticed the title of the file is changed, and based on the > observation, such change should be related to the RISCV64_DWARF_Registers.h > file? Directly using the file from last diff will not compile, so I rearrange > the file with dwarf_gpr naming convention, but seems like the functionality > is not complete. ` RISCV64_DWARF_Registers.h` has been merged to main in D130686 <https://reviews.llvm.org/D130686>, you may need rebase from main CHANGES SINCE LAST ACTION https://reviews.llvm.org/D130342/new/ https://reviews.llvm.org/D130342 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
