jrtc27 added a comment. In D110914#3036085 <https://reviews.llvm.org/D110914#3036085>, @labath wrote:
> In D110914#3036079 <https://reviews.llvm.org/D110914#3036079>, @jrtc27 wrote: > >> Is this removing this going to be a problem for RISC-V, where the >> floating-point registers could be 32-bit or 64-bit (or 128-bit in future), >> depending on which extensions you have? > > Is the size of the register fixed for the lifetime of a process ? If yes (it > sounds like this is the case), then this is not a problem, as you'd just need > to provide the correct definitions when the process is created. > > And if their size can change, then it's still should not be a problem, as you > can copy the ARM SVE model. (One of the reasons for removing this is to avoid > having two ways of doing the same thing.) Meant to reply to this (and thought I had) but somehow didn't end up doing it... Technically no if you write to hardware configuration registers to change what extensions are enabled (which limits it to kernels and higher, not userspace), but I doubt anyone expects that to work nicely in a debugger. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110914/new/ https://reviews.llvm.org/D110914 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
