omjavaid added a comment.

In D98529#2643850 <https://reviews.llvm.org/D98529#2643850>, @jasonmolenda 
wrote:

> In D98529#2631946 <https://reviews.llvm.org/D98529#2631946>, @DavidSpickett 
> wrote:
>
>> TCR_ELx begins at 1 (see `D13.2.123 TCR_EL1, Translation Control Register 
>> (EL1)` in the armarm) and covers EL0 and 1. Looking at the pseudocode access 
>> to this is undefined at EL0.
>
> I updated my local documentation & impl to only record the shared EL0/EL1 
> T0SZ value, thanks.
>
>> So the OS would have to provide you some other way to read that, I know this 
>> is missing on Linux at the moment. A user setting might be good for us 
>> supporting Linux too. (though I realise your immediate concern is MacOS)
>
> OK we may need to retain the manual setting when I upstream this, instead of 
> going with the pure Process-maintained value determined dynamically by gdb 
> packet or corefile metadata.  If this is something you need for your own 
> FixCodeAddress prelim patch, I can upstream the 
> target.process.virtual-addressable-bits setting (I think the name is fine, 
> even once Process can determine this dynamically).  We'll need to decide at 
> some point what the correct behavior is when they conflict, but if only one 
> is set the choice is straightforward.

I guess it would be important to host FixCodeAddress function in target.process 
given it may be needed for cleaning up top byte from breakpoint/watchpoint 
addresses and memory access address. I am thinking of adding FixCodeAddress to 
Process::CreateBreakpointSite and Process::ReadMemory which means it would be 
best to host a virtual-addressable-bits member in Process class and provide 
facility to update it dynamically otherwise set to architecture default. If you 
have your code handy may be you upstream it and we ll take it forward from 
there.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98529/new/

https://reviews.llvm.org/D98529

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