luismarques updated this revision to Diff 302190.
luismarques retitled this revision from "[LLDB][RISCV] Distinguish between
riscv32 and riscv64 based on ELF class" to "[LLDB][RISCV] Add RISC-V ArchSpec
and rv32/rv64 variant detection".
luismarques edited the summary of this revision.
luismarques added a reviewer: labath.
luismarques added a subscriber: labath.
luismarques added a comment.
Moved some of the ArchSpec/core bits from D62732
<https://reviews.llvm.org/D62732> to here, per @labath's suggestion.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D86292/new/
https://reviews.llvm.org/D86292
Files:
lldb/include/lldb/Utility/ArchSpec.h
lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
lldb/source/Utility/ArchSpec.cpp
lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===================================================================
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ Type: ET_EXEC
+ Machine: EM_RISCV
Index: lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
===================================================================
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+ Class: ELFCLASS32
+ Data: ELFDATA2LSB
+ Type: ET_EXEC
+ Machine: EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
{eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32,
+ ArchSpec::eCore_riscv32, "riscv32"},
+ {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64,
+ ArchSpec::eCore_riscv64, "riscv64"},
+
{eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -452,6 +457,10 @@
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
{ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
+ {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
+ {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+ ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
};
static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===================================================================
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
return arch_variant;
}
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+ uint32_t fileclass = header.e_ident[EI_CLASS];
+ switch (fileclass) {
+ case llvm::ELF::ELFCLASS32:
+ return ArchSpec::eRISCVSubType_riscv32;
+ case llvm::ELF::ELFCLASS64:
+ return ArchSpec::eRISCVSubType_riscv64;
+ default:
+ return ArchSpec::eRISCVSubType_unknown;
+ }
+}
+
static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
if (header.e_machine == llvm::ELF::EM_MIPS)
return mipsVariantFromElfFlags(header);
+ else if (header.e_machine == llvm::ELF::EM_RISCV)
+ return riscvVariantFromElfFlags(header);
return LLDB_INVALID_CPUTYPE;
}
Index: lldb/include/lldb/Utility/ArchSpec.h
===================================================================
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -99,6 +99,12 @@
eRISCV_abi_d = 0x00000020
};
+ enum RISCVSubType {
+ eRISCVSubType_unknown,
+ eRISCVSubType_riscv32,
+ eRISCVSubType_riscv64,
+ };
+
enum Core {
eCore_arm_generic,
eCore_arm_armv4,
@@ -191,6 +197,9 @@
eCore_hexagon_hexagonv4,
eCore_hexagon_hexagonv5,
+ eCore_riscv32,
+ eCore_riscv64,
+
eCore_uknownMach32,
eCore_uknownMach64,
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