omjavaid created this revision.
omjavaid added reviewers: jasonmolenda, labath, clayborg.
Herald added a subscriber: kristof.beyls.
This patch adds core definitions in lldb ArchSpecs for armv8l and armv7l cores.
There is also fix where while merging target and paltform triple we were
updating core and triple which results in new triple with unknown environment
and vendor. This fixes issues where lldb has a triple created after parsing elf
header and another from the platform and we should be using consolidated
information from both sides.
On Linux systems running on armv8 we are returned armv8l in case we are running
32bit sysroot on 64bit kernel (l for little endian).
Similarly for armv8 hardware running 32bit kernel and 32bit sysroot we are
returned armv7l. This is quite common when we run 32 bit arm using docker
container.
Also clang return target triple=armv8l-unknown-linux-gnueabihf
https://reviews.llvm.org/D69904
Files:
lldb/include/lldb/Utility/ArchSpec.h
lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
lldb/packages/Python/lldbsuite/test/make/Makefile.rules
lldb/source/Utility/ArchSpec.cpp
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -61,6 +61,8 @@
"armv6m"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
"armv7"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
+ "armv7l"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
"armv7f"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
@@ -101,6 +103,8 @@
ArchSpec::eCore_arm_arm64, "arm64"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
ArchSpec::eCore_arm_armv8, "armv8"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm,
+ ArchSpec::eCore_arm_armv8l, "armv8l"},
{eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
ArchSpec::eCore_arm_arm64_32, "arm64_32"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
@@ -878,7 +882,7 @@
IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
other.GetCore() != ArchSpec::eCore_arm_generic) {
m_core = other.GetCore();
- CoreUpdated(true);
+ CoreUpdated(false);
}
if (GetFlags() == 0) {
SetFlags(other.GetFlags());
@@ -1202,6 +1206,8 @@
case ArchSpec::eCore_arm_armv7f:
case ArchSpec::eCore_arm_armv7k:
case ArchSpec::eCore_arm_armv7s:
+ case ArchSpec::eCore_arm_armv7l:
+ case ArchSpec::eCore_arm_armv8l:
if (!enforce_exact_match) {
if (core2 == ArchSpec::eCore_arm_generic)
return true;
Index: lldb/packages/Python/lldbsuite/test/make/Makefile.rules
===================================================================
--- lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+++ lldb/packages/Python/lldbsuite/test/make/Makefile.rules
@@ -239,7 +239,7 @@
override ARCH :=
override ARCHFLAG :=
endif
- ifeq "$(ARCH)" "arm"
+ ifeq "$(findstring arm,$(ARCH))" "arm"
override ARCH :=
override ARCHFLAG :=
endif
Index: lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
===================================================================
--- lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
+++ lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
@@ -25,7 +25,7 @@
if arch in ['x86_64', 'i386']:
test_case.expect("register read eax", substrs=['eax = 0x'])
- elif arch in ['arm', 'armv7', 'armv7k']:
+ elif arch in ['arm', 'armv7', 'armv7k', 'armv8l', 'armv7l']:
test_case.expect("register read r0", substrs=['r0 = 0x'])
elif arch in ['aarch64', 'arm64', 'arm64e', 'arm64_32']:
test_case.expect("register read x0", substrs=['x0 = 0x'])
Index: lldb/include/lldb/Utility/ArchSpec.h
===================================================================
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -101,6 +101,7 @@
eCore_arm_armv6,
eCore_arm_armv6m,
eCore_arm_armv7,
+ eCore_arm_armv7l,
eCore_arm_armv7f,
eCore_arm_armv7s,
eCore_arm_armv7k,
@@ -122,6 +123,7 @@
eCore_thumbv7em,
eCore_arm_arm64,
eCore_arm_armv8,
+ eCore_arm_armv8l,
eCore_arm_arm64_32,
eCore_arm_aarch64,
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -61,6 +61,8 @@
"armv6m"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
"armv7"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
+ "armv7l"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
"armv7f"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
@@ -101,6 +103,8 @@
ArchSpec::eCore_arm_arm64, "arm64"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
ArchSpec::eCore_arm_armv8, "armv8"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm,
+ ArchSpec::eCore_arm_armv8l, "armv8l"},
{eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
ArchSpec::eCore_arm_arm64_32, "arm64_32"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
@@ -878,7 +882,7 @@
IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
other.GetCore() != ArchSpec::eCore_arm_generic) {
m_core = other.GetCore();
- CoreUpdated(true);
+ CoreUpdated(false);
}
if (GetFlags() == 0) {
SetFlags(other.GetFlags());
@@ -1202,6 +1206,8 @@
case ArchSpec::eCore_arm_armv7f:
case ArchSpec::eCore_arm_armv7k:
case ArchSpec::eCore_arm_armv7s:
+ case ArchSpec::eCore_arm_armv7l:
+ case ArchSpec::eCore_arm_armv8l:
if (!enforce_exact_match) {
if (core2 == ArchSpec::eCore_arm_generic)
return true;
Index: lldb/packages/Python/lldbsuite/test/make/Makefile.rules
===================================================================
--- lldb/packages/Python/lldbsuite/test/make/Makefile.rules
+++ lldb/packages/Python/lldbsuite/test/make/Makefile.rules
@@ -239,7 +239,7 @@
override ARCH :=
override ARCHFLAG :=
endif
- ifeq "$(ARCH)" "arm"
+ ifeq "$(findstring arm,$(ARCH))" "arm"
override ARCH :=
override ARCHFLAG :=
endif
Index: lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
===================================================================
--- lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
+++ lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
@@ -25,7 +25,7 @@
if arch in ['x86_64', 'i386']:
test_case.expect("register read eax", substrs=['eax = 0x'])
- elif arch in ['arm', 'armv7', 'armv7k']:
+ elif arch in ['arm', 'armv7', 'armv7k', 'armv8l', 'armv7l']:
test_case.expect("register read r0", substrs=['r0 = 0x'])
elif arch in ['aarch64', 'arm64', 'arm64e', 'arm64_32']:
test_case.expect("register read x0", substrs=['x0 = 0x'])
Index: lldb/include/lldb/Utility/ArchSpec.h
===================================================================
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -101,6 +101,7 @@
eCore_arm_armv6,
eCore_arm_armv6m,
eCore_arm_armv7,
+ eCore_arm_armv7l,
eCore_arm_armv7f,
eCore_arm_armv7s,
eCore_arm_armv7k,
@@ -122,6 +123,7 @@
eCore_thumbv7em,
eCore_arm_arm64,
eCore_arm_armv8,
+ eCore_arm_armv8l,
eCore_arm_arm64_32,
eCore_arm_aarch64,
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