tatyana-krasnukha updated this revision to Diff 225432.
tatyana-krasnukha added a comment.
Herald added a subscriber: wuzish.
Removed any ARC-specific logic from the ProcessGDBRemote.cpp.
It seems, there is nothing to test now;)
Repository:
rLLDB LLDB
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D55718/new/
https://reviews.llvm.org/D55718
Files:
include/lldb/Utility/ArchSpec.h
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
source/Target/Platform.cpp
source/Target/Thread.cpp
source/Utility/ArchSpec.cpp
Index: include/lldb/Utility/ArchSpec.h
===================================================================
--- include/lldb/Utility/ArchSpec.h
+++ include/lldb/Utility/ArchSpec.h
@@ -183,6 +183,8 @@
eCore_uknownMach32,
eCore_uknownMach64,
+ eCore_arc, // little endian ARC
+
kNumCores,
kCore_invalid,
Index: source/Utility/ArchSpec.cpp
===================================================================
--- source/Utility/ArchSpec.cpp
+++ source/Utility/ArchSpec.cpp
@@ -214,6 +214,7 @@
ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}
};
// Ensure that we have an entry in the g_core_definitions for each core. If you
@@ -436,6 +437,8 @@
ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, //
mips64r6el
{ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
+ {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
+ 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARC
};
static const ArchDefinition g_elf_arch_def = {
Index: source/Target/Thread.cpp
===================================================================
--- source/Target/Thread.cpp
+++ source/Target/Thread.cpp
@@ -2060,6 +2060,7 @@
case llvm::Triple::ppc64le:
case llvm::Triple::systemz:
case llvm::Triple::hexagon:
+ case llvm::Triple::arc:
m_unwinder_up.reset(new UnwindLLDB(*this));
break;
Index: source/Target/Platform.cpp
===================================================================
--- source/Target/Platform.cpp
+++ source/Target/Platform.cpp
@@ -1822,6 +1822,12 @@
trap_opcode_size = sizeof(g_aarch64_opcode);
} break;
+ case llvm::Triple::arc: {
+ static const uint8_t g_hex_opcode[] = { 0xff, 0x7f };
+ trap_opcode = g_hex_opcode;
+ trap_opcode_size = sizeof(g_hex_opcode);
+ } break;
+
// TODO: support big-endian arm and thumb trap codes.
case llvm::Triple::arm: {
// The ARM reference recommends the use of 0xe7fddefe and 0xdefe but the
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===================================================================
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -339,7 +339,7 @@
// not, we assume no limit
// build the qSupported packet
- std::vector<std::string> features = {"xmlRegisters=i386,arm,mips"};
+ std::vector<std::string> features = {"xmlRegisters=i386,arm,mips,arc"};
StreamString packet;
packet.PutCString("qSupported");
for (uint32_t i = 0; i < features.size(); ++i) {
Index: include/lldb/Utility/ArchSpec.h
===================================================================
--- include/lldb/Utility/ArchSpec.h
+++ include/lldb/Utility/ArchSpec.h
@@ -183,6 +183,8 @@
eCore_uknownMach32,
eCore_uknownMach64,
+ eCore_arc, // little endian ARC
+
kNumCores,
kCore_invalid,
Index: source/Utility/ArchSpec.cpp
===================================================================
--- source/Utility/ArchSpec.cpp
+++ source/Utility/ArchSpec.cpp
@@ -214,6 +214,7 @@
ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
+ {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"}
};
// Ensure that we have an entry in the g_core_definitions for each core. If you
@@ -436,6 +437,8 @@
ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
{ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
+ {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
+ 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARC
};
static const ArchDefinition g_elf_arch_def = {
Index: source/Target/Thread.cpp
===================================================================
--- source/Target/Thread.cpp
+++ source/Target/Thread.cpp
@@ -2060,6 +2060,7 @@
case llvm::Triple::ppc64le:
case llvm::Triple::systemz:
case llvm::Triple::hexagon:
+ case llvm::Triple::arc:
m_unwinder_up.reset(new UnwindLLDB(*this));
break;
Index: source/Target/Platform.cpp
===================================================================
--- source/Target/Platform.cpp
+++ source/Target/Platform.cpp
@@ -1822,6 +1822,12 @@
trap_opcode_size = sizeof(g_aarch64_opcode);
} break;
+ case llvm::Triple::arc: {
+ static const uint8_t g_hex_opcode[] = { 0xff, 0x7f };
+ trap_opcode = g_hex_opcode;
+ trap_opcode_size = sizeof(g_hex_opcode);
+ } break;
+
// TODO: support big-endian arm and thumb trap codes.
case llvm::Triple::arm: {
// The ARM reference recommends the use of 0xe7fddefe and 0xdefe but the
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===================================================================
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -339,7 +339,7 @@
// not, we assume no limit
// build the qSupported packet
- std::vector<std::string> features = {"xmlRegisters=i386,arm,mips"};
+ std::vector<std::string> features = {"xmlRegisters=i386,arm,mips,arc"};
StreamString packet;
packet.PutCString("qSupported");
for (uint32_t i = 0; i < features.size(); ++i) {
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