DavidSpickett wrote: Unless this fixes an existing test case, you could adapt the one from https://github.com/llvm/llvm-project/commit/9db2541d4c30100d7ccc6cc9db717df102b302d9 to work for RISC-V.
I put it in the AArch64 folder but it can be moved somewhere generic. The specific bits are the `x` register naming and the undefined encoding. https://github.com/llvm/llvm-project/pull/166531 _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
