================
@@ -13,18 +13,17 @@
class TestRV32MachOCorefile(TestBase):
NO_DEBUG_INFO_TESTCASE = True
- @skipUnlessDarwin
+ @no_debug_info_test
def test_riscv32_gpr_corefile_registers(self):
- self.build()
- create_corefile = self.getBuildArtifact("create-empty-riscv-corefile")
corefile = self.getBuildArtifact("core")
- call(create_corefile + " " + corefile, shell=True)
+ self.yaml2macho_core("riscv32-registers.yaml", corefile)
+ # call(create_corefile + " " + corefile, shell=True)
----------------
DavidSpickett wrote:
Remove commented line.
https://github.com/llvm/llvm-project/pull/153911
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