================ @@ -44,6 +43,8 @@ def test_armv7_corefile(self): self.assertTrue(exception.IsValid()) self.assertEqual(exception.GetValueAsUnsigned(), 0x00003F5C) + self.expect("x/4bx $sp-1", substrs=["0x000dffff", "0xff 0x00 0x01 0x02"]) ---------------- DavidSpickett wrote:
Comment to explain this magic. https://github.com/llvm/llvm-project/pull/147011 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits