================
@@ -228,9 +228,9 @@ static const CoreDefinition g_core_definitions[] = {
{eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
- {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
+ {eByteOrderLittle, 4, 2, 8, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
"riscv32"},
- {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
+ {eByteOrderLittle, 8, 2, 8, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
----------------
tedwoodward wrote:
> I read that RISC-V instructions are variable length in multiples of 16,
> though nothing standard uses greater than 32.
>
> So what's the logic of this change, that a really large number is very silly,
> but you do know of people using 64 bit custom instructions?
Exactly!
RISC-V instruction lengths are effectively unlimited (they talk about 192 in
the spec). I don't know of any that large (very silly, as you say). The people
working on https://github.com/quic/riscv-elf-psabi-quic-extensions told me they
have some 64 bit instructions, so I wanted to bump the max to 8 bytes.
https://github.com/llvm/llvm-project/pull/145793
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