================
@@ -157,6 +157,12 @@ let Definition = "target" in {
DefaultEnumValue<"eX86DisFlavorDefault">,
EnumValues<"OptionEnumValues(g_x86_dis_flavor_value_types)">,
Desc<"The default disassembly flavor to use for x86 or x86-64 targets.">;
+ def DisassemblyCPU: Property<"disassembly-cpu", "String">,
+ DefaultStringValue<"">,
+ Desc<"Override the CPU for disassembling. Takes the same values as the
-mcpu compiler flag.">;
+ def DisassemblyFeatures: Property<"disassembly-features", "String">,
+ DefaultStringValue<"">,
+ Desc<"Specify additional CPU features for disassembling.">;
----------------
jasonmolenda wrote:
FWIW my thought was that most e.g. RISC-V users will be specifying a CPU (a
collection of ISA extensions), using and they already had to do that when they
compiled the program so they would know the name that clang recognizes. It
seemed less common that someone would want/need to specify a set of ISA
extensions manually for a target, but an important capability to have available.
https://github.com/llvm/llvm-project/pull/115382
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