On Thu May 21 17:10:05 2026 +0800, Guoniu Zhou wrote:
> The ISI supports different numbers of virtual channels depending on the
> platform. i.MX95 supports 8 virtual channels, and i.MX8QXP/QM support 4
> virtual channels. They are used in multiple camera use cases, such as
> surround view. Other platforms (such as i.MX8/MN/MP/ULP/91/93) don't
> support virtual channels, and the VC_ID bits are marked as read-only.
>
> Reviewed-by: Frank Li <[email protected]>
> Signed-off-by: Guoniu Zhou <[email protected]>
> Reviewed-by: Laurent Pinchart <[email protected]>
> Link: https://patch.msgid.link/[email protected]
> Signed-off-by: Laurent Pinchart <[email protected]>
> Signed-off-by: Hans Verkuil <[email protected]>
Patch committed.
Thanks,
Hans Verkuil
.../media/platform/nxp/imx8-isi/imx8-isi-core.c | 3 ++
.../media/platform/nxp/imx8-isi/imx8-isi-core.h | 2 +
drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c | 17 +++++++-
drivers/media/platform/nxp/imx8-isi/imx8-isi-m2m.c | 2 +-
.../media/platform/nxp/imx8-isi/imx8-isi-pipe.c | 48 +++++++++++++++++++++-
.../media/platform/nxp/imx8-isi/imx8-isi-regs.h | 12 ++++--
6 files changed, 77 insertions(+), 7 deletions(-)
---
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
index e8545761b5ff..0ae5f35e017c 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
@@ -318,6 +318,7 @@ static const struct mxc_isi_plat_data mxc_imx95_data = {
.model = MXC_ISI_IMX95,
.num_ports = 4,
.num_channels = 8,
+ .num_vc = 8,
.reg_offset = 0x10000,
.ier_reg = &mxc_imx8_isi_ier_v2,
.set_thd = &mxc_imx8_isi_thd_v1,
@@ -329,6 +330,7 @@ static const struct mxc_isi_plat_data mxc_imx8qm_data = {
.model = MXC_ISI_IMX8QM,
.num_ports = 5,
.num_channels = 8,
+ .num_vc = 4,
.reg_offset = 0x10000,
.ier_reg = &mxc_imx8_isi_ier_qm,
.set_thd = &mxc_imx8_isi_thd_v1,
@@ -340,6 +342,7 @@ static const struct mxc_isi_plat_data mxc_imx8qxp_data = {
.model = MXC_ISI_IMX8QXP,
.num_ports = 5,
.num_channels = 6,
+ .num_vc = 4,
.reg_offset = 0x10000,
.ier_reg = &mxc_imx8_isi_ier_v2,
.set_thd = &mxc_imx8_isi_thd_v1,
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
index 7547a6559d4c..9bb4d430d15e 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
@@ -170,6 +170,7 @@ struct mxc_isi_plat_data {
enum model model;
unsigned int num_ports;
unsigned int num_channels;
+ unsigned int num_vc; /* Number of VCs, 0 = no VC support */
unsigned int reg_offset;
const struct mxc_isi_ier_reg *ier_reg;
const struct mxc_isi_set_thd *set_thd;
@@ -378,6 +379,7 @@ void mxc_isi_channel_unchain(struct mxc_isi_pipe *pipe);
void mxc_isi_channel_config(struct mxc_isi_pipe *pipe,
enum mxc_isi_input_id input,
+ unsigned int vc,
const struct v4l2_area *in_size,
const struct v4l2_area *scale,
const struct v4l2_rect *crop,
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c
b/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c
index e07eebae9e2b..6aa760ce3605 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c
@@ -305,6 +305,7 @@ static void mxc_isi_channel_set_panic_threshold(struct
mxc_isi_pipe *pipe)
static void mxc_isi_channel_set_control(struct mxc_isi_pipe *pipe,
enum mxc_isi_input_id input,
+ unsigned int vc,
bool bypass)
{
u32 val;
@@ -316,6 +317,10 @@ static void mxc_isi_channel_set_control(struct
mxc_isi_pipe *pipe,
CHNL_CTRL_SRC_TYPE_MASK | CHNL_CTRL_MIPI_VC_ID_MASK |
CHNL_CTRL_SRC_INPUT_MASK);
+ /* Clear the VC_ID_1 bit on platforms supporting more than 4 VCs. */
+ if (pipe->isi->pdata->num_vc > 4)
+ val &= ~CHNL_CTRL_VC_ID_1_MASK;
+
/*
* If no scaling or color space conversion is needed, bypass the
* channel.
@@ -342,7 +347,14 @@ static void mxc_isi_channel_set_control(struct
mxc_isi_pipe *pipe,
} else {
val |= CHNL_CTRL_SRC_TYPE(CHNL_CTRL_SRC_TYPE_DEVICE);
val |= CHNL_CTRL_SRC_INPUT(input);
- val |= CHNL_CTRL_MIPI_VC_ID(0); /* FIXME: For CSI-2 only */
+ val |= CHNL_CTRL_MIPI_VC_ID(vc); /* FIXME: For CSI-2 only */
+
+ /*
+ * On platforms with more than 4 VCs (i.MX95), the VC ID is
+ * split across VC_ID_0 (bits 7:6) and VC_ID_1 (bit 16).
+ */
+ if (pipe->isi->pdata->num_vc > 4)
+ val |= CHNL_CTRL_VC_ID_1(vc >> 2);
}
mxc_isi_write(pipe, CHNL_CTRL, val);
@@ -352,6 +364,7 @@ static void mxc_isi_channel_set_control(struct mxc_isi_pipe
*pipe,
void mxc_isi_channel_config(struct mxc_isi_pipe *pipe,
enum mxc_isi_input_id input,
+ unsigned int vc,
const struct v4l2_area *in_size,
const struct v4l2_area *scale,
const struct v4l2_rect *crop,
@@ -378,7 +391,7 @@ void mxc_isi_channel_config(struct mxc_isi_pipe *pipe,
mxc_isi_channel_set_panic_threshold(pipe);
/* Channel control */
- mxc_isi_channel_set_control(pipe, input, csc_bypass && scaler_bypass);
+ mxc_isi_channel_set_control(pipe, input, vc, csc_bypass &&
scaler_bypass);
}
void mxc_isi_channel_set_input_format(struct mxc_isi_pipe *pipe,
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-m2m.c
b/drivers/media/platform/nxp/imx8-isi/imx8-isi-m2m.c
index de398b232d74..b729eecad0fe 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-m2m.c
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-m2m.c
@@ -144,7 +144,7 @@ static void mxc_isi_m2m_device_run(void *priv)
.height = ctx->queues.cap.format.height,
};
- mxc_isi_channel_config(m2m->pipe, MXC_ISI_INPUT_MEM,
+ mxc_isi_channel_config(m2m->pipe, MXC_ISI_INPUT_MEM, 0,
&in_size, &scale, &crop,
ctx->queues.out.info->encoding,
ctx->queues.cap.info->encoding);
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c
b/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c
index 2d0843c86534..16085f23bc0b 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c
@@ -232,6 +232,47 @@ static inline struct mxc_isi_pipe *to_isi_pipe(struct
v4l2_subdev *sd)
return container_of(sd, struct mxc_isi_pipe, sd);
}
+static int mxc_isi_get_vc(struct mxc_isi_pipe *pipe)
+{
+ struct mxc_isi_crossbar *xbar = &pipe->isi->crossbar;
+ struct device *dev = pipe->isi->dev;
+ struct v4l2_mbus_frame_desc fd = { };
+ unsigned int source_pad = xbar->num_sinks + pipe->id;
+ unsigned int num_vcs;
+ unsigned int i;
+ int ret;
+
+ ret = v4l2_subdev_call(&xbar->sd, pad, get_frame_desc,
+ source_pad, &fd);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get source frame desc from pad %u\n",
+ source_pad);
+ return ret;
+ }
+
+ /* Find stream 0 in the frame descriptor. */
+ for (i = 0; i < fd.num_entries; i++) {
+ if (fd.entry[i].stream == 0)
+ break;
+ }
+
+ if (i == fd.num_entries) {
+ dev_err(dev, "Failed to find stream from source frame desc\n");
+ return -EPIPE;
+ }
+
+ num_vcs = pipe->isi->pdata->num_vc ? : 1;
+
+ /* Check virtual channel range. */
+ if (fd.entry[i].bus.csi2.vc >= num_vcs) {
+ dev_err(dev, "Virtual channel %u exceeds maximum %u\n",
+ fd.entry[i].bus.csi2.vc, num_vcs - 1);
+ return -EPIPE;
+ }
+
+ return fd.entry[i].bus.csi2.vc;
+}
+
int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe)
{
struct mxc_isi_crossbar *xbar = &pipe->isi->crossbar;
@@ -246,6 +287,7 @@ int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe)
struct v4l2_rect crop;
u32 input;
int ret;
+ int vc;
/*
* Find the connected input by inspecting the crossbar switch routing
@@ -280,8 +322,12 @@ int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe)
v4l2_subdev_unlock_state(state);
+ vc = mxc_isi_get_vc(pipe);
+ if (vc < 0)
+ return vc;
+
/* Configure the ISI channel. */
- mxc_isi_channel_config(pipe, input, &in_size, &scale, &crop,
+ mxc_isi_channel_config(pipe, input, vc, &in_size, &scale, &crop,
sink_info->encoding, src_info->encoding);
mxc_isi_channel_enable(pipe);
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h
b/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h
index 1b65eccdf0da..e795f4daf3ff 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h
@@ -6,6 +6,7 @@
#ifndef __IMX8_ISI_REGS_H__
#define __IMX8_ISI_REGS_H__
+#include <linux/bitfield.h>
#include <linux/bits.h>
/* ISI Registers Define */
@@ -19,9 +20,14 @@
#define CHNL_CTRL_CHAIN_BUF_NO_CHAIN 0
#define CHNL_CTRL_CHAIN_BUF_2_CHAIN 1
#define CHNL_CTRL_SW_RST BIT(24)
-#define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
-#define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
-#define CHNL_CTRL_MIPI_VC_ID(n) ((n) <<
6)
+/*
+ * CHNL_CTRL_BLANK_PXL: i.MX8{QM,QXP} only
+ * CHNL_CTRL_VC_ID_1, CHNL_CTRL_VC_ID_1_MASK: i.MX95 only
+ */
+#define CHNL_CTRL_BLANK_PXL(n)
FIELD_PREP(GENMASK(23, 16), (n))
+#define CHNL_CTRL_VC_ID_1(n)
FIELD_PREP(BIT(16), (n))
+#define CHNL_CTRL_VC_ID_1_MASK BIT(16)
+#define CHNL_CTRL_MIPI_VC_ID(n)
FIELD_PREP(GENMASK(7, 6), (n))
#define CHNL_CTRL_MIPI_VC_ID_MASK GENMASK(7, 6)
#define CHNL_CTRL_SRC_TYPE(n) ((n) << 4)
#define CHNL_CTRL_SRC_TYPE_MASK BIT(4)
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