On Fri May 29 15:34:58 2026 +0800, Wangao Wang wrote:
> Document the new compatible string "qcom,x1p42100-iris".
>
> Unlike SM8550 where the BSE (Bitstream Engine) is clocked implicitly
> via vcodec0_core, x1p42100 exposes a dedicated BSE clock vcodec0_bse
> that requires explicit enable/disable and frequency configuration.
> The SM8550 driver has no knowledge of this clock and therefore cannot
> operate x1p42100 hardware correctly.
>
> Reviewed-by: Bryan O'Donoghue <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Wangao Wang <[email protected]>
> Signed-off-by: Bryan O'Donoghue <[email protected]>
Patch committed.
Thanks,
Bryan O'Donoghue
.../bindings/media/qcom,sm8550-iris.yaml | 23 +++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
---
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
index 9c4b760508b5..0400ca1bff05 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,qcs8300-iris
- qcom,sm8550-iris
- qcom,sm8650-iris
+ - qcom,x1p42100-iris
reg:
maxItems: 1
@@ -41,13 +42,16 @@ properties:
- const: mmcx
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
clock-names:
+ minItems: 3
items:
- const: iface
- const: core
- const: vcodec0_core
+ - const: vcodec0_bse
firmware-name:
maxItems: 1
@@ -115,6 +119,23 @@ allOf:
maxItems: 1
reset-names:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,x1p42100-iris
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+ else:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
unevaluatedProperties: false
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