On Tue Apr 14 20:51:59 2026 +0200, Loic Poulain wrote:
> The CSID-340 block uses different register offsets for the PIX and RDI
> interfaces, but the driver previously indexed these registers directly
> with the camss port number. This happened to work for RDI because the
> port index matches the RDI register layout, but this assumption breaks
> with upcoming PIX interface support
>
> Introduce an explicit port-to-interface mapping and use the mapped iface
> index when programming CSID_CFG0 and CSID_CTRL. This replaces the
> standalone __csid_ctrl_rdi() helper and simplifies the RDI stream setup
> path.
>
> Also correct the CSID_CFG0/CTRL base offsets and clean up the code in
> preparation for full PIX path support.
>
> Like RDI, PIX outputs Bayer frames but can also achieve some image
> processing such as scaling, cropping and generating statitics (e.g.
> histogram), it also offer more flexebility in term of image alignment
> and stride. All of that can then later be leveraged to improve
> software or hardware frames post-processing.
>
> Signed-off-by: Loic Poulain <[email protected]>
> Reviewed-by: Bryan O'Donoghue <[email protected]>
> Signed-off-by: Bryan O'Donoghue <[email protected]>
Patch committed.
Thanks,
Bryan O'Donoghue
drivers/media/platform/qcom/camss/camss-csid-340.c | 37 ++++++++++++++--------
1 file changed, 23 insertions(+), 14 deletions(-)
---
diff --git a/drivers/media/platform/qcom/camss/camss-csid-340.c
b/drivers/media/platform/qcom/camss/camss-csid-340.c
index 9eee23bd81c2..183d40d59afb 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-340.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-340.c
@@ -41,7 +41,7 @@
#define CSI2_RX_CFG1_MISR_EN BIT(6)
#define CSI2_RX_CFG1_CGC_MODE BIT(7)
-#define CSID_CFG0(iface) (0x300 + 0x100
* (iface))
+#define CSID_CFG0(iface) (0x200 + 0x100
* (iface))
#define CSID_CFG0_BYTE_CNTR_EN BIT(0)
#define CSID_CFG0_TIMESTAMP_EN BIT(1)
#define CSID_CFG0_DECODE_FORMAT_MASK GENMASK(15, 12)
@@ -51,10 +51,24 @@
#define CSID_CFG0_DTID_MASK GENMASK(28, 27)
#define CSID_CFG0_ENABLE BIT(31)
-#define CSID_CTRL(iface) (0x308 + 0x100
* (iface))
+#define CSID_CTRL(iface) (0x208 + 0x100
* (iface))
#define CSID_CTRL_HALT_AT_FRAME_BOUNDARY 0
#define CSID_CTRL_RESUME_AT_FRAME_BOUNDARY 1
+#define CSID_MAX_RDI_SRC_STREAMS (MSM_CSID_MAX_SRC_STREAMS - 1)
+
+enum csid_iface {
+ CSID_IFACE_PIX,
+ CSID_IFACE_RDI0,
+ CSID_IFACE_RDI1,
+ CSID_IFACE_RDI2,
+};
+
+static enum csid_iface csid_port_iface_map[CSID_MAX_RDI_SRC_STREAMS] = {
+ [0] = CSID_IFACE_RDI0,
+ [1] = CSID_IFACE_RDI1,
+ [2] = CSID_IFACE_RDI2,
+};
static void __csid_configure_rx(struct csid_device *csid, struct
csid_phy_config *phy)
{
@@ -70,17 +84,13 @@ static void __csid_configure_rx(struct csid_device *csid,
struct csid_phy_config
writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
}
-static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
-{
- writel_relaxed(!!enable, csid->base + CSID_CTRL(rdi));
-}
-
static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable,
u8 port, u8 vc)
{
struct v4l2_mbus_framefmt *input_format =
&csid->fmt[MSM_CSID_PAD_FIRST_SRC + port];
const struct csid_format_info *format =
csid_get_fmt_entry(csid->res->formats->formats,
csid->res->formats->nformats,
input_format->code);
+ enum csid_iface iface = csid_port_iface_map[port];
u8 dt_id;
u32 val;
@@ -110,7 +120,8 @@ static void __csid_configure_rdi_stream(struct csid_device
*csid, u8 enable, u8
csid->id, enable ? "enable" : "disable", format->data_type,
port, vc);
- writel_relaxed(val, csid->base + CSID_CFG0(port));
+ writel_relaxed(val, csid->base + CSID_CFG0(iface));
+ writel_relaxed(enable, csid->base + CSID_CTRL(iface));
}
static void csid_configure_stream(struct csid_device *csid, u8 enable)
@@ -119,12 +130,10 @@ static void csid_configure_stream(struct csid_device
*csid, u8 enable)
__csid_configure_rx(csid, &csid->phy);
- /* Loop through all enabled ports and configure a stream for each */
- for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
- if (csid->phy.en_vc & BIT(i)) {
- __csid_configure_rdi_stream(csid, enable, i, 0);
- __csid_ctrl_rdi(csid, enable, i);
- }
+ /* RDIs */
+ for (i = 0; i < CSID_MAX_RDI_SRC_STREAMS; i++) {
+ if (csid->phy.en_vc & BIT(i))
+ __csid_configure_rdi_stream(csid, !!enable, i, 0);
}
}
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