On Fri, Aug 22, 2008 at 6:24 AM, Josh Boyer <[EMAIL PROTECTED]> wrote: > On Thu, Aug 21, 2008 at 10:14:15PM -0700, vb wrote: >>On Thu, Aug 21, 2008 at 7:29 PM, vb <[EMAIL PROTECTED]> wrote: >>> >>> But the main problem is that the kernel never sets up TLBs for neither >>> the peripheral device, nor the onboard flash. I don't seem to be able >>> to find the place where this is supposed to happen. I assumed that >>> ioremap_nocache would take care of that, but this is not the case. >>> >> >>well, in fact the TLB is set up as soon as an attempt to access the >>peripheral is made. The problem apparently is the fact that the TLB >>entry uses a wrong value in the nibble specifying the internal 460GT >>block... > > I'm not entirely sure what you mean here. Can you elaborate a bit more? >
I was referring to the top 4 MSB of the 36 bit address. So, I finally was able to access that device after massaging the device tree definitions for it, but the next device (in a different branch of the tree) still can not be accessed. What I see is that the tlb record is created when the access is attempted, but the top address nibble is 0 instead of 4, even though the device tree now includes 36 bit addresses with the correct top bits. I am trying to find code which configures the MMU and to understand how this whole subsystem works and where the wrong top 4 bits come from. Is there a document describing 44x powerpc memory management? /vb > josh > _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
