* Timur Tabi | 2008-03-12 10:58:21 [-0500]: >Sebastian Siewior wrote: >> Hello, >> >> I have here a MPC8544 DS board and I tried to utilise the dma >> controller. For the transfers I need set the [S|D]AHE bit in the Mode >> Register. This seems to be implemented but is currently unused in the >> driver. > >Which driver? Zhang's DMA driver? Yes, fsldma.c, that's the only one in tree for the CPU unless there are some hidden trees :)
>I haven't looked at Zhang's driver, but I just spotted this code: > >case FSL_DMA_IP_85XX: > new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; > new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; >case FSL_DMA_IP_83XX: > new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; > new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; > >(Don't let the missing "break" from FSL_DMA_IP_85XX fool you) > >So it looks like there already is a way to set the SAHE and DAHE bits. I guess >this is what you mean by "seems to be implemented but is currently unused"? Yes it is :) >> I haven't found a way how to set this bit except globally for >> the whole channel. > >Well, the SAHE bit is part of the MR register, so it can only apply to a whole >channel. This is a hardware limitation. Argh, I hoped that could be hidden at the offset 0x1c in the link descriptor which is marked as reserved. >> Is it possible to solve this nicely except dedicating one channel for >> such an operation? > >No. I need to hold src & dst each with one and two bytes makes four channels. And then I need one for normal transfers. So I guess I have to talk to my HW ppl that we have to change something :) Sebastian _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
