Hi: You want to say PPC440GP cannot be PCI slave without this non-transparent bridge because as David said its "interrupt pin register hardwired to zero" or there other reasons? I'm trying to use PPC440ep(or epx) and from its datasheet I don't see anything about this zero hardwiring. Does it mean "vanilla" PPC440ep will work?
And what did you use for PCI Host? Also, is your code available somwhere? Thanks, Leonid. -----Original Message----- From: sdeven.lee [mailto:[EMAIL PROTECTED] Sent: Thursday, September 06, 2007 7:04 PM To: David Hawkins Cc: Leonid; linuxppc-embedded Subject: Re: Re: PCI target implementation on AMCC PPC CPUs David Hawkins,您好！ I have been finished an application using AMCC PPC440GP as PCI target(slave) in the last 2 month.I use a non-transparent bridge(AMCC PCI6466) to make the device a target(slave) like david has said. ======= 2007-09-07 04:26:01 您在来信中写道：======= >Hi Leonid, > >In case they are not in the document: > >There are several fundamental problems with the AMCC 440EP acting as a >PCI target/slave; > >1. As a PCI target, there is only one way to generate > an interrupt to a host; you basically toggle the > interrupt pin. This makes it tricky to develop a > host-to-slave communications protocol, eg. its > hard to use the single interrupt to indicate various > interrupt states, eg. target-to-host buffer has > data versus host-to-target buffer has been emptied. > Ideally AMCC should have implemented mailboxes and/or > doorbell registers like any other sane PCI target > device (eg. some the Freescale processors, or any of > the PLX technologies chips). > >2. Look in the data sheet and see if you can figure out > how the host processor can generate an interrupt to > the PowerPC core ... oops, you can't. That kind of > makes it difficult to work with doesn't it. > > A work around would be to have the host write to the > GPIO register and wire a GPIO pin back to an external > interrupt pin. Then you would not be able to use any > other GPIO pin in that GPIO register since there is > no way to arbitrate host access versus PowerPC core > access. > >This was the other reason I ditched the AMCC part in favor of the >Freescale part. > >If you are looking at other parts, make sure you look in the PCI >configuration space of the processor reference manual. Many processors >have the interrupt pin register hardwired to zero, i.e., they can not >be used as target devices, only hosts. In that case you'd have to add >an intel 21555 non-transparent bridge to make the device a target. > >Cheers, >Dave > >_______________________________________________ >Linuxppc-embedded mailing list >[email protected] >https://ozlabs.org/mailman/listinfo/linuxppc-embedded = = = = = = = = = = = = = = = = = = = = 致 礼！ sdeven.lee [EMAIL PROTECTED] 2007-09-07 _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
