> But as Matt said (and later reminded me) the 405 has errata that is 405 > specific, and the 8xx and 403 half smaller cacheline size. So anything > statically linked may not operator correctly.... but yes, if you switch the > whole of userspace to soft-floating point then "in general" they should all be > compatable.
I don't know if gcc generates any code that tweaks with the cache, but if you only consider applications/libraries that use assembly routines to control the cache then it should be possible to convert the assembly code to assume 16-byte cachelines for all processors. That should work for processors with larger cachelines, with a performance penalty. I use a patch for glibc-2.1.3 that does exactly that. But I've only used it on 8xx-series, so correct me if I'm wrong. Btw - does someone know what the status is for recent glibc versions - do they work for 8xx out of the box? Thanks / magnus ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
