Eugene, Yes, TAH0 in SDR0_MFR register is enabled.
EMAC is able to reset correctly, but TAH isn't at the same location [in emac_probe()]. PHY is connected to EMAC and TAH is behind EMAC. I do not understand how the RX clock from PHY will reach TAH? Any suggestions ? Thanks, Sanjay -----Original Message----- From: Eugene Surovegin [mailto:[EMAIL PROTECTED] Sent: Thursday, May 19, 2005 2:23 PM To: Sanjay Bajaj Cc: linuxppc-embedded at ozlabs.org Subject: Re: tah reset? On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote: > While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset > (SR) bit never resets itself to 0. Does anybody know the reason for > it? Did you enable TAH0 in SDR0_MFR register? Also, I don't remember for sure, but TAH may have the same problem as EMAC, namely, it won't go out of reset if there is no RX clock from PHY. -- Eugene
