hi all,
we are using a customized board based on the reference design of
lite5200B.
The PCI bus heirarchy in the board is as follows:
|---------> DM642(TMS320C642)
OnChip-Host-Bridge(MPC5200B) ----> PCI-to-PCI Bridge (TI2250) ---|
|---------> Empty Slot
|
|---------> Empty Slot
The linux kernel used is 2.6.11.7. with u-boot-1.1.3. The problem we are
facing is that
I'm able to access the PCI Memory and I/O Region of DM642 from my Host
(MPC5200B) ie.upstream.
But when it comes to other way around ie. with Host Bridge being the PCI
slave and DM642 being the
master, the transaction is failing to complete. But not getting any
exceptions like master abort
and target abort. The BAR Configuration is as follows
Host (MPC5200B):
BAR0 -- 0x41000000 (256MB) Non prefetchable
BAR1 -- 0x00000000 (1GB) prefetchable
PCI-PCI Bridge (TI2250):
BAR0 -- 0x00000000 {Both are defaulted to 0's and are Read Only}
BAR1 -- 0x00000000
DM642:
BAR0 -- 0x40000000 (4MB) prefetchable
BAR1 -- 0x40800000 (8MB) Non prefetchable
BAR2 -- 0x00fff001 (16 bytes) I/O
If anyone can provide pointers and suggestions to overcome this
problem, it
will be of great help, as
we are stuck up with it since long time.
thanks and regards,
Ramprasad H L
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