Hi, > > I don't even know if we have the VHDL source - the peripherals are > > ready-to-go logic units that are just inserted in the FPGA design. > > > Do you use EDK to build your design?
Yes. > Is the physical address in your log the one you expect? Yes. Apparently, the hardware guy disabled the ethernet controller's "S/W reset" option in the EDK. This explains why the PPC got no ACK from OPB when writing to the reset register, and threw the data check exception. I hope that this problem is solved, when we enable that option. Thanks again to all who replied, Patrick ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
