Roland Dreier wrote:
> Is the following not possible:
That's a problem in any system design. Consider what would happen
if you had an architecture that was hardware cache coherent.
Software that writes to buffers at any time that is also a
DMA target will result in unpredictable behavior. The system
design for what you described requires a higher level of
shared memory software synchronization as it is exactly the
unpredictability that has to be prevented in any SMP design.
What you described is a real problem with cache unaligned
buffers that has to be avoided in systems that do not have
hardware cache coherency.
-- Dan
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