On Mon, Nov 07, 2005 at 04:44:32PM +0100, Joakim Tjernlund wrote: > > > Joakim! > > > > On Mon, Nov 07, 2005 at 03:32:52PM +0100, Joakim Tjernlund wrote: > > > Hi Marcelo > > > > > > [SNIP] > > > > The root of the problem are the changes against the 8xx TLB > > > > handlers introduced > > > > during v2.6. What happens is the TLBMiss handlers load the > > > > zeroed pte into > > > > the TLB, causing the TLBError handler to be invoked (thats > > > > two TLB faults per > > > > pagefault), which then jumps to the generic MM code to > > setup the pte. > > > > > > > > The bug is that the zeroed TLB is not invalidated (the same reason > > > > for the "dcbst" misbehaviour), resulting in infinite > > TLBError faults. > > > > > > > > Dan, I wonder why we just don't go back to v2.4 behaviour. > > > > > > This is one reason why it is the way it is: > > > > > http://ozlabs.org/pipermail/linuxppc-embedded/2005-January/016382.html > > > This details are little fuzzy ATM, but I think the reason for the > > > current > > > impl. was only that it was less intrusive to impl. > > > > Ah, I see. I wonder if the bug is processor specific: we > > don't have such > > changes in our v2.4 tree and never experienced such problem. > > > > It should be pretty easy to hit it right? (instruction > > pagefaults should > > fail). > > No, its pretty hard to trigger it. Read the all mails on the subject to > see why. > The one or two exception approach doesn't matter performancewise(at > least for ITLB exceptions) > I think.
Fine, let it continue the way it is then.
