On Apr 25, 2005, at 4:10 PM, Stuart Yoder wrote: > Hi. > ? > I am trying to figure out where in the PowerPC kernel the HID1 > register is updated to enable bits dealing with cache coherency in an > SMP system.?? Grepping through the arch/ppc source does not reveal > much. > ? > I have?two 7447A processors and somewhere the ABE and SYNCBE bits in > HID1?need to be turned on to enable cache coherency.?? Is supposed to > happen in the bootloader prior to the kernel running??
The expectation is that the bootloader normally handles such things. - kumar
