Andrei; FWIW, here is the code that I'm using to register the Xilinx
FB to the platform bus.
Cheers,
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
[EMAIL PROTECTED]
(403) 399-0195
--- arch/ppc/syslib/virtex_devices.c.old 2007-04-30 02:59:18.000000000 -0600
+++ arch/ppc/syslib/virtex_devices.c 2007-04-30 02:57:53.000000000 -0600
@@ -153,6 +153,26 @@
}, \
}
+/*
+ * ML300/ML403 Video Device: shortcut macro for single instance
+ */
+#define XPAR_TFT(num) { \
+ .name = "xilinxfb", \
+ .id = num, \
+ .dev.platform_data = &(struct xilinxfb_platform_data) { \
+ .use_dcr = XPAR_TFT_##num##_USE_DCR, \
+ .screen_height_mm = CONFIG_FB_XILINX_SCR_HEIGHT, \
+ .screen_width_mm = CONFIG_FB_XILINX_SCR_WIDTH, \
+ }, \
+ .num_resources = 1, \
+ .resource = (struct resource[]) { \
+ { \
+ .start = XPAR_TFT_##num##_BASEADDR, \
+ .end = XPAR_TFT_##num##_BASEADDR+7, \
+ .flags = IORESOURCE_IO, \
+ }, \
+ }, \
+}
/* UART 8250 driver platform data table */
struct plat_serial8250_port virtex_serial_platform_data[] = {
@@ -275,6 +295,12 @@
#endif
#endif
+#if defined(XPAR_TFT_0_BASEADDR)
+ XPAR_TFT(0),
+#endif
+#if defined(XPAR_TFT_1_BASEADDR)
+ XPAR_TFT(1),
+#endif
};
/* Early serial support functions */
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