The core itself for 405 will not have DCR: Device control registers - because no device control bus. Have to look at board spec for whether there is a replacement and what that is. Based on other comments you are on uncertain ground, likely defining a few things yourself. Interesting that the base header has a dep for DCRN based on that config. I assume you have UG011 doc from the Xilinx website.
Joachim Förster wrote: > > Hi all, > > PS: I tried to compile a kernel image with CONFIG_PPC4xx_DMA enabled, > but gcc complains about missing definitions in ppc4xx_dma.c ... e.g. > DCRN_DMASR (defined in ibm405.h). Well I guess I have to have > DCRN_MASR_BASE defined in xparameters_ml403.h .... but defined to what? > > > _______________________________________________ > Linuxppc-embedded mailing list > [email protected] > https://ozlabs.org/mailman/listinfo/linuxppc-embedded > > -- View this message in context: http://www.nabble.com/ML403-and-PPC4xx_DMA---tf3652591.html#a10207511 Sent from the linuxppc-embedded mailing list archive at Nabble.com. _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
