Hi,
we have
troubles with our 256 MBytes DDR SDRAM on our mpc5200B custom
board.
On this processor we
have four chips, 64 MBytes each connected via chipselects CS0 &
CS1.
When running a specific memory test under u-boot the CS1
connected RAM seems also to work fine (memcpy, memcmp, etc.). But U-Boot
disables the data cache as it partly boot-strapped from there. So it will not
use the DDR burst mode.
Now when booting our
2.4.25 Denx originated Linux Kernel (which we fetched via git a few weeks ago)
the data cache is on and we get into trouble when booting Linux (either signal
11 or signal 4 at different places, highly timing dependant). If we
setup only the RAM connected via CS0, we don't have any troubles. So I do not
suspect Linux to be the cause of the trouble.
It would be helpful
to see if this trouble is related to the DDR burst mode. Is there any
possibility to modify the Linux Kernel not to use the data cache of the mpc5200
or to disable it, so we do not use the burst
mode ?
A maybe stupid
question: the CS1 can be at the same time a GPIO, depending on the mpc5200B
setup. Could there be the possibility that the Linux kernel sets it up
differently inside some driver initialization routine, so the setup which
has been done inside U-Boot will be altered afterwards ?
Best
regards,
Daniel.
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