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Hi,
please read the following from MPC85xx UM about the
sequence on how to write CCSRBAR:
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When the e500 core is writing to CCSRBAR, it should use the following sequence: – Read the current value of CCSRBAR using a load word instruction followed by an isync. This forces all accesses to configuration space to complete. – Write the new value to CCSRBAR. – Perform a load of an address that does not access configuration space or the on-chip SRAM, but has an address mapping already in effect (for example, boot ROM). Follow this load with an isync. – Read the contents of CCSRBAR from its new location, followed by another isync instruction. **************************************** The codes between line 287-294 complete the third step above. Haiying
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